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<title>llvm-project.git/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[GISel][TableGen] Generate getRegBankFromRegClass (#99896)</title>
<updated>2024-07-25T13:41:55+00:00</updated>
<author>
<name>Kai Nacke</name>
<email>kai.peter.nacke@ibm.com</email>
</author>
<published>2024-07-25T13:41:55+00:00</published>
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<id>a79db96ec0decca4fe45579e039cf5589345b3ed</id>
<content type='text'>
Generating the mapping from a register class to a register bank is
complex:
 - there can be lots of register classes
 - the mapping may be ambiguos
- a register class can span several register banks (e.g. a register
class containing all registers)
- the type information is not enough to decide which register bank to
map to (e.g. a register class containing floating point and vector
registers, and all register can represent a f64 value)

The approach taken here is to encode the register banks in an array
indexed by the ID of the register class. To save space, the entries are
packed into chunks of size 2^n.</content>
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<pre>
Generating the mapping from a register class to a register bank is
complex:
 - there can be lots of register classes
 - the mapping may be ambiguos
- a register class can span several register banks (e.g. a register
class containing all registers)
- the type information is not enough to decide which register bank to
map to (e.g. a register class containing floating point and vector
registers, and all register can represent a f64 value)

The approach taken here is to encode the register banks in an array
indexed by the ID of the register class. To save space, the entries are
packed into chunks of size 2^n.</pre>
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</content>
</entry>
<entry>
<title>[X86][GISel] Add DU chain lookups for LOAD &amp; STORE (#87453)</title>
<updated>2024-04-16T11:06:17+00:00</updated>
<author>
<name>Malay Sanghi</name>
<email>malay.sanghi@intel.com</email>
</author>
<published>2024-04-16T11:06:17+00:00</published>
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<id>92e96c7bbacbb477265c7e5ff6c49a6de5d4ee69</id>
<content type='text'>
For G_LOAD and G_STORE we want this information during regbankselect.
Today we treat load dest as integer and insert converts.

---------

Co-authored-by: Evgenii Kudriashov &lt;evgenii.kudriashov@intel.com&gt;</content>
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<pre>
For G_LOAD and G_STORE we want this information during regbankselect.
Today we treat load dest as integer and insert converts.

---------

Co-authored-by: Evgenii Kudriashov &lt;evgenii.kudriashov@intel.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Use LocationSize for MMO getSize (#84751)</title>
<updated>2024-03-17T18:15:56+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-03-17T18:15:56+00:00</published>
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<id>601e102bdb55e12a2f791e0d68fd6f81ffc21e21</id>
<content type='text'>
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</content>
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<pre>
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel][NFC] Use GPhi wrapper in more places instead of iterating over operands.</title>
<updated>2024-01-12T06:25:53+00:00</updated>
<author>
<name>Amara Emerson</name>
<email>amara@apple.com</email>
</author>
<published>2024-01-12T04:30:05+00:00</published>
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<id>a946934a122abae22ef4610acc26daf5891b4b72</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[GISel] Make target's PartMapping, ValueMapping, and BankIDToCopyMapIdx arrays const. (#71079)</title>
<updated>2023-11-10T01:03:56+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2023-11-10T01:03:56+00:00</published>
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<id>c4821073cdba29c747c50e818cf39c269f88e4fd</id>
<content type='text'>
AMDGPU arrays were already const.</content>
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<pre>
AMDGPU arrays were already const.</pre>
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</content>
</entry>
<entry>
<title>GlobalISel: Pass MachineIRBuilder to applyMappingImpl</title>
<updated>2023-07-31T14:03:38+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-08-09T16:26:27+00:00</published>
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<id>d6f9428e46afbeeaedf2727682fa413381953511</id>
<content type='text'>
The target should not have to construct MachineIRBuilders during
RegBankSelect (we should perhaps hide the constructors for it). The
pass should own the builder setup with the desired CSE configuration
(although currently the pass does not use the CSE builder, which is
what I want to fix).

https://reviews.llvm.org/D156479
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<pre>
The target should not have to construct MachineIRBuilders during
RegBankSelect (we should perhaps hide the constructors for it). The
pass should own the builder setup with the desired CSE configuration
(although currently the pass does not use the CSE builder, which is
what I want to fix).

https://reviews.llvm.org/D156479
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC</title>
<updated>2023-01-14T07:12:48+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2023-01-14T06:57:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=79858d1908b53560941b7d8f4d98e5ac781c674b'/>
<id>79858d1908b53560941b7d8f4d98e5ac781c674b</id>
<content type='text'>
Use isPhysical/isVirtual methods.
</content>
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<pre>
Use isPhysical/isVirtual methods.
</pre>
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</content>
</entry>
<entry>
<title>[Target] use getSubtarget&lt;&gt; instead of static_cast&lt;&gt;(getSubtarget())</title>
<updated>2022-05-26T18:22:41+00:00</updated>
<author>
<name>Zongwei Lan</name>
<email>lanzongwei541@gmail.com</email>
</author>
<published>2022-05-26T18:22:41+00:00</published>
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<id>ad73ce318ef901545fa82d57a609c71af787e1e1</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D125391
</content>
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<pre>
Differential Revision: https://reviews.llvm.org/D125391
</pre>
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</content>
</entry>
<entry>
<title>[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)</title>
<updated>2022-03-28T05:22:37+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2022-03-28T05:22:37+00:00</published>
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<id>62128719684261745c1f9c49d4811c930d13570a</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Revert "[llvm] Remove redundant member initialization (NFC)"</title>
<updated>2022-01-03T19:28:47+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2022-01-03T19:28:47+00:00</published>
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<id>e5947760c2e568c2090841a452aa8469cc66f6c8</id>
<content type='text'>
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

  warning: base class ‘class llvm::MCParsedAsmOperand’ should be
  explicitly initialized in the copy constructor [-Wextra]
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<pre>
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

  warning: base class ‘class llvm::MCParsedAsmOperand’ should be
  explicitly initialized in the copy constructor [-Wextra]
</pre>
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</content>
</entry>
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