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<title>llvm-project.git/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)</title>
<updated>2024-03-23T12:12:44+00:00</updated>
<author>
<name>Evgenii Kudriashov</name>
<email>evgenii.kudriashov@intel.com</email>
</author>
<published>2024-03-23T12:12:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d365a45cb3eaa640b09874fb7984a6a69683c773'/>
<id>d365a45cb3eaa640b09874fb7984a6a69683c773</id>
<content type='text'>
Here we introduce three new GMIR instructions to cover a set of trap
intrinsics. The idea behind it is that generic intrinsics shouldn't be
used with G_INTRINSIC opcode.

These new instructions can match perfectly with existing trap ISD nodes.
It allows X86, AArch64, RISCV and Mips to reuse SelectionDAG patterns for
selection and avoid manual selection. However AMDGPU is an exception. It
selects traps during legalization regardless SelectionDAG or GlobalISel.

Since there are not many places where traps are used, this change
attempts to clean up all the usages of G_INTRINSIC with trap intrinsics. So,
there is no stage when both G_TRAP and
G_INTRINSIC_W_SIDE_EFFECTS(@llvm.trap) are allowed.</content>
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<pre>
Here we introduce three new GMIR instructions to cover a set of trap
intrinsics. The idea behind it is that generic intrinsics shouldn't be
used with G_INTRINSIC opcode.

These new instructions can match perfectly with existing trap ISD nodes.
It allows X86, AArch64, RISCV and Mips to reuse SelectionDAG patterns for
selection and avoid manual selection. However AMDGPU is an exception. It
selects traps during legalization regardless SelectionDAG or GlobalISel.

Since there are not many places where traps are used, this change
attempts to clean up all the usages of G_INTRINSIC with trap intrinsics. So,
there is no stage when both G_TRAP and
G_INTRINSIC_W_SIDE_EFFECTS(@llvm.trap) are allowed.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Use LocationSize for MMO getSize (#84751)</title>
<updated>2024-03-17T18:15:56+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-03-17T18:15:56+00:00</published>
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<id>601e102bdb55e12a2f791e0d68fd6f81ffc21e21</id>
<content type='text'>
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</content>
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<pre>
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel][AArch64] Tail call libcalls. (#74929)</title>
<updated>2024-01-03T07:59:36+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-01-03T07:59:36+00:00</published>
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<id>d659bd1635326cfc52460e9a43e08953906903bb</id>
<content type='text'>
This tries to allow libcalls to be tail called, using a similar method
to DAG where the type is checked to make sure they match, and if so the
backend, through lowerCall checks that the tailcall is valid for all
arguments.</content>
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<pre>
This tries to allow libcalls to be tail called, using a similar method
to DAG where the type is checked to make sure they match, and if so the
backend, through lowerCall checks that the tailcall is valid for all
arguments.</pre>
</div>
</content>
</entry>
<entry>
<title>Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"</title>
<updated>2023-07-27T09:19:17+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2023-07-27T09:19:17+00:00</published>
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<id>7c760b224bc4581a7a962ae7ded098a260d19500</id>
<content type='text'>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
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<pre>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
</pre>
</div>
</content>
</entry>
<entry>
<title>Use llvm::bit_cast (NFC)</title>
<updated>2023-02-14T09:22:12+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2023-02-14T09:22:12+00:00</published>
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<id>64dad4ba9af603330458a7673e39a873afdf3d4d</id>
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</content>
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<pre>
</pre>
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</entry>
<entry>
<title>MachineIRBuilder: Rename buildMerge. NFC</title>
<updated>2023-01-13T08:32:58+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2023-01-09T10:59:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f95a5fbe7ce1ddc890868a2b4720b4561af672cf'/>
<id>f95a5fbe7ce1ddc890868a2b4720b4561af672cf</id>
<content type='text'>
`buildMerge` may build a G_MERGE_VALUES, G_BUILD_VECTOR or
G_CONCAT_VECTORS. Rename it to `buildMergeLikeInstr`.

This is a follow-up suggested in https://reviews.llvm.org/D140964

Differential Revision: https://reviews.llvm.org/D141372
</content>
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<pre>
`buildMerge` may build a G_MERGE_VALUES, G_BUILD_VECTOR or
G_CONCAT_VECTORS. Rename it to `buildMergeLikeInstr`.

This is a follow-up suggested in https://reviews.llvm.org/D140964

Differential Revision: https://reviews.llvm.org/D141372
</pre>
</div>
</content>
</entry>
<entry>
<title>[Target] use getSubtarget&lt;&gt; instead of static_cast&lt;&gt;(getSubtarget())</title>
<updated>2022-05-26T18:22:41+00:00</updated>
<author>
<name>Zongwei Lan</name>
<email>lanzongwei541@gmail.com</email>
</author>
<published>2022-05-26T18:22:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ad73ce318ef901545fa82d57a609c71af787e1e1'/>
<id>ad73ce318ef901545fa82d57a609c71af787e1e1</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D125391
</content>
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<pre>
Differential Revision: https://reviews.llvm.org/D125391
</pre>
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</content>
</entry>
<entry>
<title>Cleanup includes: DebugInfo &amp; CodeGen</title>
<updated>2022-03-12T16:26:40+00:00</updated>
<author>
<name>serge-sans-paille</name>
<email>sguelton@redhat.com</email>
</author>
<published>2022-03-09T21:29:31+00:00</published>
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<id>ed98c1b37661b0795a5e34517941485f0f0688d1</id>
<content type='text'>
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332
</content>
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<pre>
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332
</pre>
</div>
</content>
</entry>
<entry>
<title>Mips/GlobalISel: Use accurate memory LLTs</title>
<updated>2021-07-02T00:08:14+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2021-06-11T16:02:38+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>GlobalISel: Use LLT in memory legality queries</title>
<updated>2021-06-30T21:44:13+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2021-06-09T00:22:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=28f2f66200c5719a637d857387922c91d8b12c34'/>
<id>28f2f66200c5719a637d857387922c91d8b12c34</id>
<content type='text'>
This enables proper lowering of non-byte sized loads. We still aren't
faithfully preserving memory types everywhere, so the legality checks
still only consider the size.
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<pre>
This enables proper lowering of non-byte sized loads. We still aren't
faithfully preserving memory types everywhere, so the legality checks
still only consider the size.
</pre>
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</content>
</entry>
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