Add a check before emitting the teq instruction to check whether the
divisor is a non-zero immediate value.

Fix #130629.

This focuses on the common interfaces and tablegen. More changes
are needed to individual targets.

Identified with misc-include-cleaner.

We encountered this problem in Zig, causing all of our
`mips(el)-linux-gnueabi*` tests to fail:
https://github.com/ziglang/zig/issues/21215

For these unusual cases, let's just bail in `MipsFastISel` since
`MipsTargetLowering` can handle them fine.

Note: I don't have commit access.

We need to mask the SRL result to 8 bits before ORing in the SLL. This
is needed in case bits 23:16 of the input aren't zero. They will have
been shifted into bits 15:8.

We don't need to AND the result with 0xffff. It's ok if the upper 16
bits of the register are garbage.

Fixes #103035.

This is a preparation for changing the data structure of MBBMap.

This iteration drops hunks where the loop body adds more elements.

This reverts commit 3614f65a7ba9d925010e3316a1d93bcebc632178.

fixupImmediateBr seems to resize ImmBranches.

Finally addresses https://reviews.llvm.org/D148769#4311232 :)

No behavior change.