Prepare for removing MipsMCExpr. Adopt the newer naming convention (S_)
used by AMDGPU/WebAssembly/VE/M68k/PowerPC/LoongArch/RISCV.

Follow the X86 renaming.

> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM’s usage, and fits the assembler's role seamlessly.

In addition, rename MipsMCExpr::getKind, which confusingly shadows the base class getKind.

e.g.
`addiu   $t2, $t3, .Lend-.Lstart-4`
used by libdragon/boot/boot_trampoline.S

To make this work, update a few places:

* AsmParser: When matching a isSImm/isUImm, consider an expression
  that does not evaluate to an assemble-time constant an immediate.
* MCCodeEmitter: If this is an I-type instruction and the expression
  does not evaluate to an assemble-time constant, append a
  `fixup_Mips_AnyImm16`.
  TODO: in MipsInstrInfo.td, more `Operand` should switch from the
  default `getMachineOpValue` to `getImmOpValue` like RISCV.
* AsmBackend: If the expression does not evaluate to a constant
  with assembler layout information, report "unknown relocation type"
  like X86. If the result is not within [-32768,65535] (the bound gas
  uses when parsing a constant integer for ADDIU)

Fix #126531

Pull Request: https://github.com/llvm/llvm-project/pull/127581

Use id() to get rid of some implicit conversions.

Note that llvm::support::endianness has been renamed to
llvm::endianness while becoming an enum class as opposed to an
enum. This patch replaces support::{big,little,native} with
llvm::endianness::{big,little,native}.