llvm-project.git/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [ARM] Remove unused includes (NFC) (#116155) 2024-11-14T07:11:14+00:00 Kazu Hirata kazu@google.com 2024-11-14T07:11:14+00:00 5be43db9b17e7cfc9e987f257221b0926551eb6e Identified with misc-include-cleaner. 
Identified with misc-include-cleaner.
 [CodeGen] Use LocationSize for MMO getSize (#84751) 2024-03-17T18:15:56+00:00 David Green david.green@arm.com 2024-03-17T18:15:56+00:00 601e102bdb55e12a2f791e0d68fd6f81ffc21e21 This is part of #70452 that changes the type used for the external interface of MMO to LocationSize as opposed to uint64_t. This means the constructors take LocationSize, and convert ~UINT64_C(0) to LocationSize::beforeOrAfter(). The getSize methods return a LocationSize. This allows us to be more precise with unknown sizes, not accidentally treating them as unsigned values, and in the future should allow us to add proper scalable vector support but none of that is included in this patch. It should mostly be an NFC. Global ISel is still expected to use the underlying LLT as it needs, and are not expected to see unknown sizes for generic operations. Most of the changes are hopefully fairly mechanical, adding a lot of getValue() calls and protecting them with hasValue() where needed. 
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.
 Cleanup codegen includes 2022-03-16T07:43:00+00:00 serge-sans-paille sguelton@redhat.com 2022-03-15T09:54:19+00:00 989f1c72e0f4236ac35a35cc9998ea34bc62d5cd This is a (fixed) recommit of https://reviews.llvm.org/D121169 after: 1061034926 before: 1063332844 Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681 
This is a (fixed) recommit of https://reviews.llvm.org/D121169

after:  1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681
Revert "Cleanup codegen includes" 2022-03-10T12:59:22+00:00 Nico Weber thakis@chromium.org 2022-03-10T12:54:41+00:00 a278250b0f85949d4f98e641786e5eb2b540c6b0 This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169 
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169
Cleanup codegen includes 2022-03-10T09:00:30+00:00 serge-sans-paille sguelton@redhat.com 2022-03-07T23:25:52+00:00 7f230feeeac8a67b335f52bd2e900a05c6098f20 after: 1061034926 before: 1063332844 Differential Revision: https://reviews.llvm.org/D121169 
after:  1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169
[Target] Remove redundant member initialization (NFC) 2022-01-07T06:01:44+00:00 Kazu Hirata kazu@google.com 2022-01-07T06:01:44+00:00 f3a344d2125fa37e59bae1b0874442c650a19607 Identified with readability-redundant-member-init. 
Identified with readability-redundant-member-init.
Revert "[llvm] Remove redundant member initialization (NFC)" 2022-01-03T19:28:47+00:00 Kazu Hirata kazu@google.com 2022-01-03T19:28:47+00:00 e5947760c2e568c2090841a452aa8469cc66f6c8 This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3. This patch causes gcc to issue a lot of warnings like: warning: base class ‘class llvm::MCParsedAsmOperand’ should be explicitly initialized in the copy constructor [-Wextra] 
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.

This patch causes gcc to issue a lot of warnings like:

  warning: base class ‘class llvm::MCParsedAsmOperand’ should be
  explicitly initialized in the copy constructor [-Wextra]
[llvm] Remove redundant member initialization (NFC) 2022-01-02T00:18:18+00:00 Kazu Hirata kazu@google.com 2022-01-02T00:18:18+00:00 fd4808887ee47f3ec8a030e9211169ef4fb094c3 Identified with readability-redundant-member-init. 
Identified with readability-redundant-member-init.
[ARM] Add bank conflict hazarding 2020-12-23T14:00:59+00:00 David Penry david.penry@arm.com 2020-12-23T14:00:59+00:00 a9f14cdc6203c05425f8b17228ff368f7fd9ae29 Adds ARMBankConflictHazardRecognizer. This hazard recognizer looks for a few situations where the same base pointer is used and then checks whether the offsets lead to a bank conflict. Two parameters are also added to permit overriding of the target assumptions: arm-data-bank-mask=<int> - Mask of bits which are to be checked for conflicts. If all these bits are equal in the offsets, there is a conflict. arm-assume-itcm-bankconflict=<bool> - Assume that there will be bank conflicts on any loads to a constant pool. This hazard recognizer is enabled for Cortex-M7, where the Technical Reference Manual states that there are two DTCM banks banked using bit 2 and one ITCM bank. Differential Revision: https://reviews.llvm.org/D93054 
Adds ARMBankConflictHazardRecognizer. This hazard recognizer
looks for a few situations where the same base pointer is used and
then checks whether the offsets lead to a bank conflict. Two
parameters are also added to permit overriding of the target
assumptions:

arm-data-bank-mask=<int> - Mask of bits which are to be checked for
conflicts.  If all these bits are equal in the offsets, there is a
conflict.
arm-assume-itcm-bankconflict=<bool> - Assume that there will be bank
conflicts on any loads to a constant pool.

This hazard recognizer is enabled for Cortex-M7, where the Technical
Reference Manual states that there are two DTCM banks banked using bit
2 and one ITCM bank.

Differential Revision: https://reviews.llvm.org/D93054
[Schedule] Add a MultiHazardRecognizer 2020-10-26T08:06:17+00:00 David Green david.green@arm.com 2020-10-26T08:06:17+00:00 61bc18de0b2edf8659053b06d73dfd2563143572 This adds a MultiHazardRecognizer and starts to make use of it in the ARM backend. The idea of the class is to allow multiple independent hazard recognizers to be added to a single base MultiHazardRecognizer, allowing them to all work in parallel without requiring them to be chained into subclasses. They can then be added or not based on cpu or subtarget features, which will become useful in the ARM backend once more hazard recognizers are being used for various things. This also renames ARMHazardRecognizer to ARMHazardRecognizerFPMLx in the process, to more clearly explain what that recognizer is designed for. Differential Revision: https://reviews.llvm.org/D72939 
This adds a MultiHazardRecognizer and starts to make use of it in the
ARM backend. The idea of the class is to allow multiple independent
hazard recognizers to be added to a single base MultiHazardRecognizer,
allowing them to all work in parallel without requiring them to be
chained into subclasses. They can then be added or not based on cpu or
subtarget features, which will become useful in the ARM backend once
more hazard recognizers are being used for various things.

This also renames ARMHazardRecognizer to ARMHazardRecognizerFPMLx in the
process, to more clearly explain what that recognizer is designed for.

Differential Revision: https://reviews.llvm.org/D72939