llvm-project.git/llvm/lib/Target/AMDGPU/VOPDInstructions.td, branch users/mingmingl-llvm/samplefdo-profile-format Unnamed repository; edit this file 'description' to name the repository. [AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516) 2025-09-09T14:54:18+00:00 Joe Nash joseph.nash@amd.com 2025-09-09T14:54:18+00:00 9c858f568062e44dd5ac8ad5280fae4eb75ce69d These can be represented by the same definition. It is just a RegisterOperand wrapper for a VGPR register class with a DecoderMethod override. NFC. 
These can be represented by the same definition. It is just a
RegisterOperand wrapper for a VGPR register class with a DecoderMethod
override.
NFC.
 [TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098) 2025-08-30T04:44:20+00:00 Sergei Barannikov barannikov88@gmail.com 2025-08-30T04:44:20+00:00 cc5e8967ab1ae04ccbb6a8678dcd4ef0d5c5ccdf I believe it became no-op with the removal of the "positionally encoded operands" functionality (b87dc356 is the last commit in the series). There are no changes in the generated files. 
I believe it became no-op with the removal of the "positionally encoded
operands" functionality (b87dc356 is the last commit in the series).

There are no changes in the generated files.
 [AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602) 2025-07-10T21:15:01+00:00 Stanislav Mekhanoshin rampitec@users.noreply.github.com 2025-07-10T21:15:01+00:00 7920dff39406c2af3859d8e316c8f098526d6af3 






[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)
2025-05-09T09:10:53+00:00

Ivan Kosarev
ivan.kosarev@amd.com

2025-05-09T09:10:53+00:00

66d3980b53086f787d0236814c3cc34fc568e25e

All immediates are deferred now.




All immediates are deferred now.






[AMDGPU] Add GFX12 assembler/disassembler support for v_dual_dot2acc_* (#119211)
2024-12-09T15:12:08+00:00

Jay Foad
jay.foad@amd.com

2024-12-09T15:12:08+00:00

d1cf86fe53bd89e107f8348a117754b59b4ffca5

Do for GFX12 what #118984 did for GFX11.




Do for GFX12 what #118984 did for GFX11.






[AMDGPU] Add assembler/disassembler support for v_dual_dot2acc_f32_bf16 (#118984)
2024-12-09T09:47:22+00:00

Jay Foad
jay.foad@amd.com

2024-12-09T09:47:22+00:00

f9d6d46a8edfac7421a4b010eb216f793669bef1

There is still no codegen support because the corresponding 
v_dot2c_f32_bf16 instruction is not supported on GFX11.




There is still no codegen support because the corresponding 
v_dot2c_f32_bf16 instruction is not supported on GFX11.






[AMDGPU] Update VOP instructions for GFX12 (#74853)
2023-12-12T10:38:24+00:00

Mariusz Sikora
mariusz.sikora@amd.com

2023-12-12T10:38:24+00:00

a97028ac511c2cda607a1e93c3b11d654cbdbf72

Co-authored-by: Mirko Brkusanin <Mirko.Brkusanin@amd.com>




Co-authored-by: Mirko Brkusanin <Mirko.Brkusanin@amd.com>






[AMDGPU] Make VOPD insts with a FMAMK or FMAMK component have a fixed size
2023-08-14T11:32:41+00:00

Mirko Brkusanin
Mirko.Brkusanin@amd.com

2023-08-14T11:16:27+00:00

6e86ab7e4ff92a3d18a20e61fe632a5fb2766af2

This fixes a failure from the expensive-checks buildbot

Differential Revision: https://reviews.llvm.org/D157857





This fixes a failure from the expensive-checks buildbot

Differential Revision: https://reviews.llvm.org/D157857







[AMDGPU] Fix delay alu for VOPD with src2acc
2022-10-25T17:11:17+00:00

Joe Nash
Joseph.Nash@amd.com

2022-10-20T19:03:46+00:00

01b8140d3aac50ad4c00246bddab8646a61016ed

V_FMAC_F32 and V_DOT2C_F32_F16 have a dummy src2 operand tied to vdst to
inform passes that the instructions read the dst operand. The VOPD
versions of these instructions lacked the dummy operand, which was a
problem for inserting s_delay_alu.
Introduce the dummy src2 operand on the VOPD versions, and fix the VOPD operand
tracking logic to account for it.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D136629





V_FMAC_F32 and V_DOT2C_F32_F16 have a dummy src2 operand tied to vdst to
inform passes that the instructions read the dst operand. The VOPD
versions of these instructions lacked the dummy operand, which was a
problem for inserting s_delay_alu.
Introduce the dummy src2 operand on the VOPD versions, and fix the VOPD operand
tracking logic to account for it.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D136629







[AMDGPU] gfx11 VOPD instructions MC support
2022-06-24T15:08:39+00:00

Joe Nash
Joseph.Nash@amd.com

2022-05-25T18:09:11+00:00

07b7fada73da5e371607cf42b60b5d1a2706ad1c

VOPD is a new encoding for dual-issue instructions for use in wave32.
This patch includes MC layer support only.

A VOPD instruction is constituted of an X component (for which there are
13 possible opcodes) and a Y component (for which there are the 13 X
opcodes plus 3 more). Most of the complexity in defining and parsing
a VOPD operation arises from the possible different total numbers of
operands and deferred parsing of certain operands depending on the
constituent X and Y opcodes.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D128218





VOPD is a new encoding for dual-issue instructions for use in wave32.
This patch includes MC layer support only.

A VOPD instruction is constituted of an X component (for which there are
13 possible opcodes) and a Y component (for which there are the 13 X
opcodes plus 3 more). Most of the complexity in defining and parsing
a VOPD operation arises from the possible different total numbers of
operands and deferred parsing of certain operands depending on the
constituent X and Y opcodes.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D128218