llvm-project.git/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp, branch users/koachan/spr/main.sparcias-enable-parseforallfeatures-in-matchoperandparserimpl

[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)

2024-06-18T14:44:14+00:00

Our other tools support them, so we want them in LLVM
assembler/disassembler too.

[AMDGPU][MC] Disable sendmsg SYSMSG_OP_HOST_TRAP_ACK on gfx9+ (#90203)

2024-05-07T11:38:58+00:00

This is no longer supported as of gfx9. Fixes #52903

This commit also includes some refactoring of sendmsg operand parsing:
  - Use CustomOperand for sendmsg operations, this allows them to be
    conditionally available based on a STI check (and automatically in
    sync with SIDefines.h).
  - Move CustomOperand table lookups from AMDGPUBaseInfo to
    AMDGPUAsmUtils. This cleans up an awkward interface where
    AMDGPUAsmUtils defined a table/size as globals that AMDGPUBaseInfo
    had to loop over.
  - Clean up a few of the operand lookup functions while moving them.

[AMDGPU] Fix GFX11 sendmsg codes (#85299)

2024-03-15T16:46:58+00:00

The code MSG_RTN_GET_TBA_TO_PC was missing, and the next code is off by
1 as a result.

[AMDGPU] Update sendmsg types for GFX12 (#74888)

2023-12-11T09:02:00+00:00

[AMDGPU] Update hardware registers for GFX12 (#74445)

2023-12-06T10:04:52+00:00

[AMDGPU] Add GFX11 HW_REG_PERF_SNAPSHOT_*

2023-02-10T20:28:14+00:00

These are similar to hardware registers already added for GFX940,
but with different numbers and slightly different names.

Differential Revision: https://reviews.llvm.org/D143740

[AMDGPU] sendmsg(MSG_ORDERED_PS_DONE) is not supported on GFX11

2023-01-26T08:51:07+00:00

Differential Revision: https://reviews.llvm.org/D142537

[AMDGPU] gfx11 scalar alu instructions

2022-05-17T17:35:41+00:00

MC layer support for SOP(scalar alu operations) including encoding
support for s_delay_alu and s_sendmsg_rtn.

Contributors:
Jay Foad 

Patch 7/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125319

Reviewed By: #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D125498

[AMDGPU] gfx11 BUF Instructions

2022-05-16T13:41:40+00:00

Includes MachineCode layer support and tests, and MIR tests not requiring
CodeGen pass changes.
Includes a small change in SMInstructions.td to correct encoded bits.

Contributors:
Petar Avramovic 
Dmitry Preobrazhensky 

Depends on D125316

Patch 6/N for upstreaming of AMDGPU gfx11 architecture.

Reviewed By: dp, Petar.Avramovic

Differential Revision: https://reviews.llvm.org/D125319

[AMDGPU][MC][GFX10] Added syntactic sugar for s_waitcnt_depctr operand

2022-04-07T14:03:44+00:00

Added the following helpers:

    depctr_hold_cnt(...)
    depctr_sa_sdst(...)
    depctr_va_vdst(...)
    depctr_va_sdst(...)
    depctr_va_ssrc(...)
    depctr_va_vcc(...)
    depctr_vm_vsrc(...)

Differential Revision: https://reviews.llvm.org/D123022