llvm-project.git/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp, branch users/koachan/spr/main.sparcias-enable-parseforallfeatures-in-matchoperandparserimpl

AMDGPU: Materialize bitwise not of inline immediates (#95960)

2024-06-21T22:40:59+00:00

If we have a bitwise negated inline immediate, we can materialize
it with s_not_b32/v_not_b32. This mirrors the current bitreverse
handling.
    
As a side effect, we also now handle the bitreversed FP immediate
case.
    
One test shows some VOPD regressions on gfx11 which should
probably be fixed. Previously the 2 v_mov_b32 could be packed,
but now the mismatched opcode + mov can't. This problem already
already existed for the bfrev case, it just happens more often now.

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24T13:24:14+00:00

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

AMDGPU/NFC: Remove some bits from TSFlags (#81525)

2024-02-12T21:43:48+00:00

- AMDGPU/NFC: Purge SOPK_ZEXT from TSFlags
  - Moved to helper function in SIInstInfo
- AMDGPU/NFC: Purge VOPAsmPrefer32Bit from TSFlags
  - This flag did not make sense / remnants of something else I think

[AMDGPU] Remove s_cmpk_* for GFX12 (#75497)

2023-12-14T21:10:53+00:00

No GFX12 encoding was added for these. This patch adds tests that they
are not recognized by the assembler and defends against generating them
in codegen.

[AMDGPU] Shrink to SOPK with 32-bit signed literals (#70263)

2023-10-26T07:26:54+00:00

A literal like 0xffff8000 is valid to be used as KIMM in a SOPK
instruction, but at the moment our checks expect it to be fully sign
extended to a 64-bit signed integer. This is not required since all
cases which are being shrunk only accept 32-bit operands.

We need to sign extend the operand to 64-bit though so it passes the
verifier and properly printed.

[AMDGPU] Remove legality checks from imm folding in shrink. NFCI. (#69539)

2023-10-19T10:52:28+00:00

The immediate legality checks are now embedded into the
isOperandLegal(). It is not needed to check it again.

[AMDGPU] [NFC] Fixed a typo in SIShrinkInstructions.cpp

2023-07-21T10:05:19+00:00

Reviewed By: pravinjagtap

Differential Revision: https://reviews.llvm.org/D155785

[AMDGPU][GFX11] Legalize and select partial NSA MIMG instructions

2023-02-23T12:33:34+00:00

If more registers are needed for VAddr then the NSA format allows then the
final register can act as a contigous set of remaining addresses. Update
legalizer to pack register for this new format and allow instruction
selection to use NSA encoding when number of addresses exceeds max size.
Also update SIShrinkInstructions to handle partial NSA.

Differential Revision: https://reviews.llvm.org/D144034

[CodeGen] Make more use of MachineOperand::getOperandNo. NFC.

2023-02-07T11:50:57+00:00

Differential Revision: https://reviews.llvm.org/D143252

[Target] Use llvm::count{l,r}_{zero,one} (NFC)

2023-01-28T17:23:07+00:00