llvm-project.git/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp, branch main

[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)

2025-09-16T03:22:14+00:00

Create utility mechanism for finding wave size dependent opcodes used to
manipulate exec/lane masks.

[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)

2025-02-20T12:05:56+00:00

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03T12:07:54+00:00

Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

2024-07-10T11:34:48+00:00

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24T13:24:14+00:00

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

[MC] Add MCRegisterInfo::regunits for iteration over register units

2023-06-16T02:39:50+00:00

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098

[AMDGPU] Recompute liveness in SIOptimizeExecMaskingPreRA

2023-05-09T07:02:22+00:00

Instead of ad-hoc updating liveness, recompute it completely for the affected register.

This does not affect any existing test and fixes an edge case that
caused a "Non-empty but used interval" error in the register allocator
due to how the pass updated liveranges. It created a "isolated" live-through
segment.

Overall this change just seems to be a net positive with no side effect observed. There may be a compile time impact but it's expected to be minimal.

Fixes SWDEV-388279

Reviewed By: critson

Differential Revision: https://reviews.llvm.org/D150105

[AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

2023-04-08T07:39:21+00:00

This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

Differential Revision: https://reviews.llvm.org/D147721

[AMDGPU] Fix comment in SIOptimizeExecMaskingPreRA

2023-04-07T10:07:50+00:00

[AMDGPU] Fix liveness in the SIOptimizeExecMaskingPreRA.cpp

2023-02-05T20:21:28+00:00

If a condition register def happens past the newly created use
we do not properly update LIS. It has two problems:

1) We do not extend defining segment to the end of its block
   marking it a live-out (this is regression after
   https://reviews.llvm.org/rG09d38dd7704a52e8ad2d5f8f39aaeccf107f4c56)

2) We do not extend use segment to the beginning of the use block
   marking it a live-in.

Fixes: SWDEV-379563

Differential Revision: https://reviews.llvm.org/D143302