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<title>llvm-project.git/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)</title>
<updated>2025-09-16T03:22:14+00:00</updated>
<author>
<name>Carl Ritson</name>
<email>carl.ritson@amd.com</email>
</author>
<published>2025-09-16T03:22:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fdb06d9792afc8121e77b367cb6dce0be29b2b5b'/>
<id>fdb06d9792afc8121e77b367cb6dce0be29b2b5b</id>
<content type='text'>
Create utility mechanism for finding wave size dependent opcodes used to
manipulate exec/lane masks.</content>
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<pre>
Create utility mechanism for finding wave size dependent opcodes used to
manipulate exec/lane masks.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (#128928)</title>
<updated>2025-02-28T14:41:05+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-02-28T14:41:05+00:00</published>
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<content type='text'>
True16 Add OpSel when optimizing exec mask

True16 VOPCX have the opsel argument. Add it when we create these
instructions in SIOptimizeExecMasking.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
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True16 Add OpSel when optimizing exec mask

True16 VOPCX have the opsel argument. Add it when we create these
instructions in SIOptimizeExecMasking.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[TableGen] Emit OpName as an enum class instead of a namespace (#125313)</title>
<updated>2025-02-12T16:19:30+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-02-12T16:19:30+00:00</published>
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<id>bee9664970d51df3f4e1d298d1bcb95bba364e17</id>
<content type='text'>
- Change InstrInfoEmitter to emit OpName as an enum class
  instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are 
  OpNames vs just operand indices and should help avoid
  bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
  enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
  to conform to the new definition of OpName (mostly
  mechanical changes).</content>
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- Change InstrInfoEmitter to emit OpName as an enum class
  instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are 
  OpNames vs just operand indices and should help avoid
  bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
  enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
  to conform to the new definition of OpName (mostly
  mechanical changes).</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)</title>
<updated>2025-01-20T11:04:01+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2025-01-20T11:04:01+00:00</published>
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<id>96c4f978d0fd1339262a350e118375ee4bf5fc57</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)</title>
<updated>2024-07-17T20:11:00+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-07-17T20:11:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=63fae3ed656241a1d6a19c3e773ecc9bfff3e182'/>
<id>63fae3ed656241a1d6a19c3e773ecc9bfff3e182</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)</title>
<updated>2024-07-10T11:34:48+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2024-07-10T11:34:48+00:00</published>
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<id>abde52aa667118d18e9551ab87a15b95c267b3b6</id>
<content type='text'>
- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.</content>
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- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.</pre>
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</content>
</entry>
<entry>
<title>Reapply "Convert many LivePhysRegs uses to LiveRegUnits" (#84338)</title>
<updated>2024-03-08T13:35:00+00:00</updated>
<author>
<name>AtariDreams</name>
<email>83477269+AtariDreams@users.noreply.github.com</email>
</author>
<published>2024-03-08T13:35:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7c21495fee927359d642793d2eeb24696a301262'/>
<id>7c21495fee927359d642793d2eeb24696a301262</id>
<content type='text'>
This only converts the instances where all that is needed is to change
the variable type name.

Basically, anything that involves a function that LiveRegUnits does not
directly have was skipped to play it safe.

Reverts
https://github.com/llvm/llvm-project/commit/7a0e222a17058a311b69153d0b6f1b4459414778</content>
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<pre>
This only converts the instances where all that is needed is to change
the variable type name.

Basically, anything that involves a function that LiveRegUnits does not
directly have was skipped to play it safe.

Reverts
https://github.com/llvm/llvm-project/commit/7a0e222a17058a311b69153d0b6f1b4459414778</pre>
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</content>
</entry>
<entry>
<title>Revert "Convert many LivePhysRegs uses to LiveRegUnits (#83905)"</title>
<updated>2024-03-07T08:20:26+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-03-07T08:16:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7a0e222a17058a311b69153d0b6f1b4459414778'/>
<id>7a0e222a17058a311b69153d0b6f1b4459414778</id>
<content type='text'>
This reverts commit 2a13422b8bcee449405e3ebff957b4020805f91c.

It was causing test failures on the expensive check builders.
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This reverts commit 2a13422b8bcee449405e3ebff957b4020805f91c.

It was causing test failures on the expensive check builders.
</pre>
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</content>
</entry>
<entry>
<title>Convert many LivePhysRegs uses to LiveRegUnits (#83905)</title>
<updated>2024-03-06T05:08:14+00:00</updated>
<author>
<name>AtariDreams</name>
<email>83477269+AtariDreams@users.noreply.github.com</email>
</author>
<published>2024-03-06T05:08:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2a13422b8bcee449405e3ebff957b4020805f91c'/>
<id>2a13422b8bcee449405e3ebff957b4020805f91c</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Detect kills in register sets when trying to form V_CMPX instructions. (#68293)</title>
<updated>2023-11-02T09:36:27+00:00</updated>
<author>
<name>Thomas Symalla</name>
<email>5754458+tsymalla@users.noreply.github.com</email>
</author>
<published>2023-11-02T09:36:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=18839aec4ed1977142444d650bf6c74c705fee44'/>
<id>18839aec4ed1977142444d650bf6c74c705fee44</id>
<content type='text'>
During the SIOptimizeExecMasking pass, we try to form V_CMPX
instructions by detecting S_AND_SAVEEXEC and V_MOV instructions.
Generally, we require the input operand of the V_MOV, which is the input
operand to the to-be-formed V_CMPX, to be alive. This is forced by
clearing the kill flags on the operand after V_CMPX has been generated.

However, if we have a kill of a register set that contains said
register, this will not be detected by clearKillFlags.
With this change, possible additional kill-flag candidates will be
detected during the final call to findInstrBackwards and then, the kill
flag will be removed to keep all registers in the set alive.

Co-authored-by: Thomas Symalla &lt;thomas.symalla@amd.com&gt;</content>
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During the SIOptimizeExecMasking pass, we try to form V_CMPX
instructions by detecting S_AND_SAVEEXEC and V_MOV instructions.
Generally, we require the input operand of the V_MOV, which is the input
operand to the to-be-formed V_CMPX, to be alive. This is forced by
clearing the kill flags on the operand after V_CMPX has been generated.

However, if we have a kill of a register set that contains said
register, this will not be detected by clearKillFlags.
With this change, possible additional kill-flag candidates will be
detected during the final call to findInstrBackwards and then, the kill
flag will be removed to keep all registers in the set alive.

Co-authored-by: Thomas Symalla &lt;thomas.symalla@amd.com&gt;</pre>
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