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<title>llvm-project.git/llvm/lib/Target/AMDGPU/SIInstrInfo.td, branch users/mingmingl-llvm/samplefdo-profile-format</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)</title>
<updated>2025-09-09T14:54:18+00:00</updated>
<author>
<name>Joe Nash</name>
<email>joseph.nash@amd.com</email>
</author>
<published>2025-09-09T14:54:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9c858f568062e44dd5ac8ad5280fae4eb75ce69d'/>
<id>9c858f568062e44dd5ac8ad5280fae4eb75ce69d</id>
<content type='text'>
These can be represented by the same definition. It is just a
RegisterOperand wrapper for a VGPR register class with a DecoderMethod
override.
NFC.</content>
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<pre>
These can be represented by the same definition. It is just a
RegisterOperand wrapper for a VGPR register class with a DecoderMethod
override.
NFC.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Remove unused getEquivalentAGPRClass (#157671)</title>
<updated>2025-09-09T14:13:01+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-09T14:13:01+00:00</published>
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<id>5044128ce268b7c25c269491271e4c2a45627313</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Remove getLdStRegisterOperandForSize (#157216)</title>
<updated>2025-09-08T08:57:57+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-08T08:57:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4c6a56225f3982ab2de7f8acb8d8560079a830c8'/>
<id>4c6a56225f3982ab2de7f8acb8d8560079a830c8</id>
<content type='text'>
The AV operand classes should be used directly at the top level
of the load/store definitions. Inline the remaining use into the
strange MUBUF TFE vs. non-TFE usecase, which needed a special case
for 16-bit operands anyway.</content>
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<pre>
The AV operand classes should be used directly at the top level
of the load/store definitions. Inline the remaining use into the
strange MUBUF TFE vs. non-TFE usecase, which needed a special case
for 16-bit operands anyway.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Use RegisterOperand for MIMG class data operands (#157215)</title>
<updated>2025-09-08T08:20:36+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-08T08:20:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8cc77e748f4f6a0ddfb1e218f9e1e5c4ec4d5e6c'/>
<id>8cc77e748f4f6a0ddfb1e218f9e1e5c4ec4d5e6c</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Directly use align2 classes in gfx90a mimg operands</title>
<updated>2025-09-06T01:05:33+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-06T01:05:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=be1510f9bb2d6502172626991ee72d88bcc1bd94'/>
<id>be1510f9bb2d6502172626991ee72d88bcc1bd94</id>
<content type='text'>
 (#157037)

This regresses the assembler diagnostics. I made some attempts
at avoiding this, but it turns out the way we manage these
is really wrong. We're completely ignoring the reported missing
features from MatchInstructionImpl and also don't have properly
configured predicates to automatically get the message.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
 (#157037)

This regresses the assembler diagnostics. I made some attempts
at avoiding this, but it turns out the way we manage these
is really wrong. We're completely ignoring the reported missing
features from MatchInstructionImpl and also don't have properly
configured predicates to automatically get the message.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Really fix operands for global vgpr rtn atomics (#156989)</title>
<updated>2025-09-05T22:41:15+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-05T22:41:15+00:00</published>
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<id>06ce03005b95d5b244dd88aa4fc21a00f7b246a0</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Change BUF classes to use RegisterOperand parameters (#157053)</title>
<updated>2025-09-05T13:32:40+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-05T13:32:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=12631c8035bff88e705ec4a7383fd81474b4f68d'/>
<id>12631c8035bff88e705ec4a7383fd81474b4f68d</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Change DS classes to use RegisterOperand parameters (#156580)</title>
<updated>2025-09-04T05:14:04+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-04T05:14:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c5a8841a2a085bce32381d99ae22dc0acadf6a37'/>
<id>c5a8841a2a085bce32381d99ae22dc0acadf6a37</id>
<content type='text'>
Start stripping out the uses of getLdStRegisterOperand. This
added a confusing level of indirection where the class at the
definition point was not the actual class used. This was also
pulling in the AV class usage for targets where it isn't
relevant. This was also inflexible for special cases.

Also fixes using default arguments which only served to wrap the
class argument in a RegisterOperand.

This should be done for all the memory instructions.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Start stripping out the uses of getLdStRegisterOperand. This
added a confusing level of indirection where the class at the
definition point was not the actual class used. This was also
pulling in the AV class usage for targets where it isn't
relevant. This was also inflexible for special cases.

Also fixes using default arguments which only served to wrap the
class argument in a RegisterOperand.

This should be done for all the memory instructions.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Add agpr variants of multi-data DS instructions (#156420)</title>
<updated>2025-09-04T00:13:36+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-04T00:13:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1959e12e7dd84f388547c3f85af7b919f2253377'/>
<id>1959e12e7dd84f388547c3f85af7b919f2253377</id>
<content type='text'>
The instruction definitions for loads and stores do not
accurately model the operand constraints of loads and stores
with AGPRs. They use AV register classes, plus a hack
a hack in getRegClass/getOpRegClass to avoid using AGPRs or
AV classes with the multiple operand cases, but it did not
consider the 3 operand case.

Model this correctly by using separate all-VGPR and all-AGPR
variants for the cases with multiple data operands.

This does regress the assembler errors on gfx908 for the
multi-operand cases. It now reports a generic operand
invalid error for GPU instead of the specific message
that agpr loads and stores aren't supported.

In the future AMDGPURewriteAGPRCopyMFMA should be taught
to replace the VGPR forms with the AGPR ones.

Most of the diff is fighting the DS pseudo structure. The
mnemonic was being used as the key to SIMCInstr, which is a
collision in the AGPR case. We also need to go out of our way
to make sure we are using the gfx9+ variants of the pseudos
without the m0 use. The DS multiclasses could use a lot of
cleanup.

Fixes #155777</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The instruction definitions for loads and stores do not
accurately model the operand constraints of loads and stores
with AGPRs. They use AV register classes, plus a hack
a hack in getRegClass/getOpRegClass to avoid using AGPRs or
AV classes with the multiple operand cases, but it did not
consider the 3 operand case.

Model this correctly by using separate all-VGPR and all-AGPR
variants for the cases with multiple data operands.

This does regress the assembler errors on gfx908 for the
multi-operand cases. It now reports a generic operand
invalid error for GPU instead of the specific message
that agpr loads and stores aren't supported.

In the future AMDGPURewriteAGPRCopyMFMA should be taught
to replace the VGPR forms with the AGPR ones.

Most of the diff is fighting the DS pseudo structure. The
mnemonic was being used as the key to SIMCInstr, which is a
collision in the AGPR case. We also need to go out of our way
to make sure we are using the gfx9+ variants of the pseudos
without the m0 use. The DS multiclasses could use a lot of
cleanup.

Fixes #155777</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][NFC] Reduce diff between downstream branch (#155779)</title>
<updated>2025-08-28T09:06:36+00:00</updated>
<author>
<name>Mariusz Sikora</name>
<email>mariusz.sikora@amd.com</email>
</author>
<published>2025-08-28T09:06:36+00:00</published>
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<id>d8285dfb3390c522f1b597cf8642ce78bded3115</id>
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<pre>
</pre>
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