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<title>llvm-project.git/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp, branch users/nico/python-2</title>
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<title>AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)</title>
<updated>2025-07-01T18:08:49+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-07-01T18:08:49+00:00</published>
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These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</content>
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These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</pre>
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<entry>
<title>AMDGPU: Avoid report_fatal_error for unsupported ds_ordered_count (#145172)</title>
<updated>2025-06-26T05:06:05+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-26T05:06:05+00:00</published>
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<entry>
<title>[AMDGPU][True16][CodeGen] do not legalize t16 operand during user scan (#145450)</title>
<updated>2025-06-25T03:49:22+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-06-25T03:49:22+00:00</published>
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<content type='text'>
The legalize t16 operand function could insert a reg_sequence which
modify the user list of the targetted register, and we should not call
it in the middle of an user list iteration</content>
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<pre>
The legalize t16 operand function could insert a reg_sequence which
modify the user list of the targetted register, and we should not call
it in the middle of an user list iteration</pre>
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</entry>
<entry>
<title>[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (#145152)</title>
<updated>2025-06-22T19:52:05+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>rampitec@users.noreply.github.com</email>
</author>
<published>2025-06-22T19:52:05+00:00</published>
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<entry>
<title>[AMDGPU][True16][Codegen] keep srcmod/clamp/omod from v_s_xxx_f16 when moved to VALU (#144781)</title>
<updated>2025-06-19T13:26:45+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-06-19T13:26:45+00:00</published>
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<content type='text'>
https://github.com/llvm/llvm-project/pull/141152 causes an issue in
v_s_xxx_f16 lowering in both true16/fake16 flow.

V_S_XXX_F16 are special insts which has scalar input/output but in VALU
VOP3 format. Need to keep the srcmod/clamp/omod when lower it to its
corresponding VALU inst with vector input/output.</content>
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<pre>
https://github.com/llvm/llvm-project/pull/141152 causes an issue in
v_s_xxx_f16 lowering in both true16/fake16 flow.

V_S_XXX_F16 are special insts which has scalar input/output but in VALU
VOP3 format. Need to keep the srcmod/clamp/omod when lower it to its
corresponding VALU inst with vector input/output.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] v_s_xxx_f16 t16 mode handling in movetoVALU process (#141152)</title>
<updated>2025-06-10T19:36:44+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-06-10T19:36:44+00:00</published>
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<id>e48731bc03419f133a85b50571a368a889c6dab2</id>
<content type='text'>
Add op_sel for v_s_xxx_f16 when move them to VALU

update a few related codegen test for gfx12 in true16 mode</content>
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<pre>
Add op_sel for v_s_xxx_f16 when move them to VALU

update a few related codegen test for gfx12 in true16 mode</pre>
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</entry>
<entry>
<title>[AMDGPU] Move S_ADD_U64_PSEUDO handling into getVALUOp. NFC. (#142934)</title>
<updated>2025-06-05T15:49:24+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-06-05T15:49:24+00:00</published>
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<content type='text'>
S_ADD_U64_PSEUDO and S_SUB_U64_PSEUDO are not "special cases" so can be
handled in getVALUOp instead of moveToVALUImpl.</content>
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<pre>
S_ADD_U64_PSEUDO and S_SUB_U64_PSEUDO are not "special cases" so can be
handled in getVALUOp instead of moveToVALUImpl.</pre>
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</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] legalize 16bit and 32bit use-def chain for moveToVALU in si-fix-sgpr-lowering (#138734)</title>
<updated>2025-06-04T13:53:10+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-06-04T13:53:10+00:00</published>
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<id>b668b6439acb9057faadd788c9351a7d20bf140e</id>
<content type='text'>
Two changes in this patch:
1. Covered another case in legalizeOperandVALUt16 functions and the COPY
lowering, when SALU16 is used by SALU32, need to insert a reg_sequence
after moved to valu (previously only considered SALU32 used by SALU16
case)
2. Moved the useMI analysis into addUsersToMoveVALUList. Legalize the
targetted operand when needed.

Turn on frem test with true16 mode for gfx1150 which is failing before
this patch. A few bitcast tests also impacted by this change with some
v_mov being replaced to dual mov</content>
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<pre>
Two changes in this patch:
1. Covered another case in legalizeOperandVALUt16 functions and the COPY
lowering, when SALU16 is used by SALU32, need to insert a reg_sequence
after moved to valu (previously only considered SALU32 used by SALU16
case)
2. Moved the useMI analysis into addUsersToMoveVALUList. Legalize the
targetted operand when needed.

Turn on frem test with true16 mode for gfx1150 which is failing before
this patch. A few bitcast tests also impacted by this change with some
v_mov being replaced to dual mov</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Remove redundant operand folding checks (#140587)</title>
<updated>2025-05-29T17:38:45+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-29T17:38:45+00:00</published>
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<content type='text'>
This was pre-filtering out a specific situation from being
added to the fold candidate list. The operand legality will
ultimately be checked with isOperandLegal before the fold is
performed, so I don't see the plus in pre-filtering this one
case.</content>
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<pre>
This was pre-filtering out a specific situation from being
added to the fold candidate list. The operand legality will
ultimately be checked with isOperandLegal before the fold is
performed, so I don't see the plus in pre-filtering this one
case.</pre>
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</entry>
<entry>
<title>Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)</title>
<updated>2025-05-28T19:26:39+00:00</updated>
<author>
<name>Justin Bogner</name>
<email>mail@justinbogner.com</email>
</author>
<published>2025-05-28T19:26:39+00:00</published>
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This annotates the `Twine` passed to the constructors of the various
DiagnosticInfo subclasses with `[[clang::lifetimebound]]`, which causes
us to warn when we would try to print the twine after it had already
been destructed.

We also update `DiagnosticInfoUnsupported` to hold a `const Twine &amp;`
like all of the other DiagnosticInfo classes, since this warning allows
us to clean up all of the places where it was being used incorrectly.</content>
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<pre>
This annotates the `Twine` passed to the constructors of the various
DiagnosticInfo subclasses with `[[clang::lifetimebound]]`, which causes
us to warn when we would try to print the twine after it had already
been destructed.

We also update `DiagnosticInfoUnsupported` to hold a `const Twine &amp;`
like all of the other DiagnosticInfo classes, since this warning allows
us to clean up all of the places where it was being used incorrectly.</pre>
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