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<title>llvm-project.git/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU] SIInsertHardClause: add configurable clause length limit (#142343)</title>
<updated>2025-06-04T06:00:34+00:00</updated>
<author>
<name>Carl Ritson</name>
<email>carl.ritson@amd.com</email>
</author>
<published>2025-06-04T06:00:34+00:00</published>
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<id>e47e4d8ae6062adba8985606b6b01c6743f68da2</id>
<content type='text'>
Add command line and function attribute configuration of hard clause
length limit (within hardware maximum).
This allows performance tuning for shaders which benefit from smaller
clauses.</content>
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<pre>
Add command line and function attribute configuration of hard clause
length limit (within hardware maximum).
This allows performance tuning for shaders which benefit from smaller
clauses.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Treat image_msaa_load as a sampler operation (#141726)</title>
<updated>2025-05-28T10:56:05+00:00</updated>
<author>
<name>Carl Ritson</name>
<email>carl.ritson@amd.com</email>
</author>
<published>2025-05-28T10:56:05+00:00</published>
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<id>34b6285735c999d2fab77b0ff8e5b497d86df3af</id>
<content type='text'>
While image_msaa_load does not take a sampler, it can behave as if it
does on some hardware. This has implications for wait counting and
clausing.</content>
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<pre>
While image_msaa_load does not take a sampler, it can behave as if it
does on some hardware. This has implications for wait counting and
clausing.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Classify FLAT instructions as VMEM (#137148)</title>
<updated>2025-05-07T07:20:52+00:00</updated>
<author>
<name>Robert Imschweiler</name>
<email>robert.imschweiler@amd.com</email>
</author>
<published>2025-05-07T07:20:52+00:00</published>
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<id>e55172f139a21f3d6da932787a0b221b53eab2cb</id>
<content type='text'>
Also adapt hazard and wait handling.</content>
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<pre>
Also adapt hazard and wait handling.</pre>
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</content>
</entry>
<entry>
<title>[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)</title>
<updated>2025-04-18T14:46:31+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-04-18T14:46:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078'/>
<id>f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078</id>
<content type='text'>
This change removes the uint64_t constructor on LocationSize
preventing implicit conversion, and fixes up the using APIs to adapt to
the change. Note that I'm adding a couple of explicit conversion points
on routines where passing in a fixed offset as an integer seems likely
to have well understood semantics.

We had an unfortunate case which arose if you tried to pass a TypeSize
value to a parameter of LocationSize type. We'd find the implicit
conversion path through TypeSize -&gt; uint64_t -&gt; LocationSize which works
just fine for fixed values, but looses information and fails assertions
if the TypeSize was scalable. This change breaks the first link in that
implicit conversion chain since that seemed to be the easier one.</content>
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<pre>
This change removes the uint64_t constructor on LocationSize
preventing implicit conversion, and fixes up the using APIs to adapt to
the change. Note that I'm adding a couple of explicit conversion points
on routines where passing in a fixed offset as an integer seems likely
to have well understood semantics.

We had an unfortunate case which arose if you tried to pass a TypeSize
value to a parameter of LocationSize type. We'd find the implicit
conversion path through TypeSize -&gt; uint64_t -&gt; LocationSize which works
just fine for fixed values, but looses information and fails assertions
if the TypeSize was scalable. This change breaks the first link in that
implicit conversion chain since that seemed to be the easier one.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][NPM] Port SIInsertHardClauses to NPM (#130062)</title>
<updated>2025-03-25T10:03:32+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2025-03-25T10:03:32+00:00</published>
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<id>f8e908a0edce2ed8b835af9aad3993a20bb8f5ce</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)</title>
<updated>2024-03-06T17:40:13+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-03-06T17:40:13+00:00</published>
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<id>44be5a7fdc20a7f90d63dc18699a470e900bd3ba</id>
<content type='text'>
This is another part of #70452 which makes getMemOperandsWithOffsetWidth
use a LocationSize for Width, as opposed to the unsigned it currently
uses. The advantages on it's own are not super high if
getMemOperandsWithOffsetWidth usually uses known sizes, but if the
values can come from an MMO it can help be more accurate in case they
are Unknown (and in the future, scalable).</content>
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<pre>
This is another part of #70452 which makes getMemOperandsWithOffsetWidth
use a LocationSize for Width, as opposed to the unsigned it currently
uses. The advantages on it's own are not super high if
getMemOperandsWithOffsetWidth usually uses known sizes, but if the
values can come from an MMO it can help be more accurate in case they
are Unknown (and in the future, scalable).</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Make maximum hard clause size a subtarget feature (#81287)</title>
<updated>2024-02-15T19:58:31+00:00</updated>
<author>
<name>Krzysztof Drewniak</name>
<email>Krzysztof.Drewniak@amd.com</email>
</author>
<published>2024-02-15T19:58:31+00:00</published>
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<id>b4972341462b4e892b4f24abe3f6970054f28b16</id>
<content type='text'>
gfx11 chips may, in some conditions, behave incorrectly with S_CLAUSE
instructions (hard clauses) containing more than 32 operations (that is,
whose arguments exceed 0x1f). However, gfx10 targets will work
successfully with clauses of up to length 63.

Therefore, define the MaxHardClauseLength property on GCNSubtarget and
make it a subtarget feature via tablegen, thus allowing us to specify,
both now and in the future, the maximum viable size of clauses on
various hardware from the tablegen definition. If MaxHardClauseLength is
0, which is the default, the hardware does not support hard clauses.</content>
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<pre>
gfx11 chips may, in some conditions, behave incorrectly with S_CLAUSE
instructions (hard clauses) containing more than 32 operations (that is,
whose arguments exceed 0x1f). However, gfx10 targets will work
successfully with clauses of up to length 63.

Therefore, define the MaxHardClauseLength property on GCNSubtarget and
make it a subtarget feature via tablegen, thus allowing us to specify,
both now and in the future, the maximum viable size of clauses on
various hardware from the tablegen definition. If MaxHardClauseLength is
0, which is the default, the hardware does not support hard clauses.</pre>
</div>
</content>
</entry>
<entry>
<title>[MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldClusterMemOps (#73778)</title>
<updated>2023-12-06T15:30:48+00:00</updated>
<author>
<name>Alex Bradbury</name>
<email>asb@igalia.com</email>
</author>
<published>2023-12-06T15:30:48+00:00</published>
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<id>b7173652163fa968e1df47fa211ce8a549489abd</id>
<content type='text'>
These are picked up from getMemOperandsWithOffsetWidth but weren't then
being passed through to shouldClusterMemOps, which forces backends to
collect the information again if they want to use the kind of heuristics
typically used for the similar shouldScheduleLoadsNear function (e.g.
checking the offset is within 1 cache line).

This patch just adds the parameters, but doesn't attempt to use them.
There is potential to use them in the current PPC and AArch64
shouldClusterMemOps implementation, and I intend to use the offset in
the heuristic for RISC-V. I've left these for future patches in the
interest of being as incremental as possible.

As noted in the review and in an inline FIXME, an ElementCount-style abstraction may later be used to condense these two parameters to one argument. ElementCount isn't quite suitable as it doesn't support negative offsets.</content>
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<pre>
These are picked up from getMemOperandsWithOffsetWidth but weren't then
being passed through to shouldClusterMemOps, which forces backends to
collect the information again if they want to use the kind of heuristics
typically used for the similar shouldScheduleLoadsNear function (e.g.
checking the offset is within 1 cache line).

This patch just adds the parameters, but doesn't attempt to use them.
There is potential to use them in the current PPC and AArch64
shouldClusterMemOps implementation, and I intend to use the offset in
the heuristic for RISC-V. I've left these for future patches in the
interest of being as incremental as possible.

As noted in the review and in an inline FIXME, an ElementCount-style abstraction may later be used to condense these two parameters to one argument. ElementCount isn't quite suitable as it doesn't support negative offsets.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Update SIInsertHardClauses for GFX11</title>
<updated>2022-06-09T20:29:56+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2022-06-09T10:38:48+00:00</published>
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<content type='text'>
Changes for GFX11:
- Clauses may not mix instructions of different types, and there are
  more types. For example image instructions with and without a sampler
  are now different types.
- The max size of a clause is explicitly documented as 63 instructions.
  Previously it was implicitly assumed to be 64. This is such a tiny
  difference that it does not seem worth making it conditional on the
  subtarget.
- It can be beneficial to clause stores as well as loads.

Differential Revision: https://reviews.llvm.org/D127391
</content>
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<pre>
Changes for GFX11:
- Clauses may not mix instructions of different types, and there are
  more types. For example image instructions with and without a sampler
  are now different types.
- The max size of a clause is explicitly documented as 63 instructions.
  Previously it was implicitly assumed to be 64. This is such a tiny
  difference that it does not seem worth making it conditional on the
  subtarget.
- It can be beneficial to clause stores as well as loads.

Differential Revision: https://reviews.llvm.org/D127391
</pre>
</div>
</content>
</entry>
<entry>
<title>Cleanup codegen includes</title>
<updated>2022-03-16T07:43:00+00:00</updated>
<author>
<name>serge-sans-paille</name>
<email>sguelton@redhat.com</email>
</author>
<published>2022-03-15T09:54:19+00:00</published>
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<id>989f1c72e0f4236ac35a35cc9998ea34bc62d5cd</id>
<content type='text'>
This is a (fixed) recommit of https://reviews.llvm.org/D121169

after:  1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681
</content>
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<pre>
This is a (fixed) recommit of https://reviews.llvm.org/D121169

after:  1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681
</pre>
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</entry>
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