<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm-project.git/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)</title>
<updated>2025-11-21T15:17:55+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-11-21T15:17:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0b6db777ba9821bc17b969ddf6fefee54519c4f4'/>
<id>0b6db777ba9821bc17b969ddf6fefee54519c4f4</id>
<content type='text'>
Fix a problem exposed by #166483 using AV classes in more places.
`isVectorRegister` only accepts registers of VGPR or AGPR classes.
`hasVectorRegisters` additionally accepts the combined AV classes.

Fixes: #168761</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix a problem exposed by #166483 using AV classes in more places.
`isVectorRegister` only accepts registers of VGPR or AGPR classes.
`hasVectorRegisters` additionally accepts the combined AV classes.

Fixes: #168761</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)</title>
<updated>2025-11-14T17:18:43+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-14T17:18:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=cfc74dddeffd3e53c7fdb90593db01a01cffda8f'/>
<id>cfc74dddeffd3e53c7fdb90593db01a01cffda8f</id>
<content type='text'>
Fixes another verifier error after introducing AV registers.
Also fixes not clearing the subregister index if there was
one.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fixes another verifier error after introducing AV registers.
Also fixes not clearing the subregister index if there was
one.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Constrain readfirstlane operand to vgpr_32 (#168001)</title>
<updated>2025-11-14T16:40:18+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-14T16:40:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c6ee2d9860363a4fdc6dcd65107a8663a0eceb52'/>
<id>c6ee2d9860363a4fdc6dcd65107a8663a0eceb52</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)</title>
<updated>2025-11-14T11:00:57+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-11-14T11:00:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=72c69aefbae8bfb087622e642acbd0cba7578747'/>
<id>72c69aefbae8bfb087622e642acbd0cba7578747</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)</title>
<updated>2025-09-16T03:22:14+00:00</updated>
<author>
<name>Carl Ritson</name>
<email>carl.ritson@amd.com</email>
</author>
<published>2025-09-16T03:22:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fdb06d9792afc8121e77b367cb6dce0be29b2b5b'/>
<id>fdb06d9792afc8121e77b367cb6dce0be29b2b5b</id>
<content type='text'>
Create utility mechanism for finding wave size dependent opcodes used to
manipulate exec/lane masks.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Create utility mechanism for finding wave size dependent opcodes used to
manipulate exec/lane masks.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Restrict scale operands of WMMA to low 256 VGPRs (#157526)</title>
<updated>2025-09-08T22:44:51+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-09-08T22:44:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b0ee92be94746e05e9c015fcc6f7533e6b222685'/>
<id>b0ee92be94746e05e9c015fcc6f7533e6b222685</id>
<content type='text'>
These cannot accept high registers.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
These cannot accept high registers.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)</title>
<updated>2025-08-18T14:01:29+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-08-18T14:01:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=07eb7b76928d6873c60859a0339591ed9e0f512a'/>
<id>07eb7b76928d6873c60859a0339591ed9e0f512a</id>
<content type='text'>
This patch replaces SmallSet&lt;T *, N&gt; with SmallPtrSet&lt;T *, N&gt;.  Note
that SmallSet.h "redirects" SmallSet to SmallPtrSet for pointer
element types:

  template &lt;typename PointeeType, unsigned N&gt;
class SmallSet&lt;PointeeType*, N&gt; : public SmallPtrSet&lt;PointeeType*, N&gt;
{};

We only have 140 instances that rely on this "redirection", with the
vast majority of them under llvm/. Since relying on the redirection
doesn't improve readability, this patch replaces SmallSet with
SmallPtrSet for pointer element types.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch replaces SmallSet&lt;T *, N&gt; with SmallPtrSet&lt;T *, N&gt;.  Note
that SmallSet.h "redirects" SmallSet to SmallPtrSet for pointer
element types:

  template &lt;typename PointeeType, unsigned N&gt;
class SmallSet&lt;PointeeType*, N&gt; : public SmallPtrSet&lt;PointeeType*, N&gt;
{};

We only have 140 instances that rely on this "redirection", with the
vast majority of them under llvm/. Since relying on the redirection
doesn't improve readability, this patch replaces SmallSet with
SmallPtrSet for pointer element types.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Fix sgpr to vreg_1 copy analysis (#149181)</title>
<updated>2025-07-18T05:08:50+00:00</updated>
<author>
<name>Jorn Tuyls</name>
<email>jorn.tuyls@gmail.com</email>
</author>
<published>2025-07-18T05:08:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=03fe1a493d55cfc27a32ee3064639b86cb54d16a'/>
<id>03fe1a493d55cfc27a32ee3064639b86cb54d16a</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Handle av imm pseudo in si-fix-sgpr-copies phi fold (#149263)</title>
<updated>2025-07-18T00:03:37+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-07-18T00:03:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a131ce960332db56cd1729c4829bf2694ddcb3ea'/>
<id>a131ce960332db56cd1729c4829bf2694ddcb3ea</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)</title>
<updated>2025-07-09T20:17:14+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-07-09T20:17:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0d2b47ae4a01fd97fe479806a45a535ad347eb63'/>
<id>0d2b47ae4a01fd97fe479806a45a535ad347eb63</id>
<content type='text'>
When true16 is enabled, isel start to emit sgpr_lo16 register when a
trunc/sext i16/i32 is generated, or a salu32 is used by vgpr16 or vice
versa. And this causes a problem as sgpr_lo16 is not fully supported in
the pipeline.

True16 mode works fine in -O3 mode since folding pass remove sgpr_lo16
from the pipeline. However it hit a problem in -O0 mode as folding pass
is skipped.

This patch did:
1. stop emitting sgpr_lo16 from isel
2. update codegen pattern to split uniformed/divergent pattern for
i16/i32 conversion
3. update fix-sgpr-copy pass to address legalization requirement in
true16 mode, update fix-sgpr-copies-f16-true16.mir
test to include all possible combinations

This patch is tested with cts and downstream repo with -O0 testing</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When true16 is enabled, isel start to emit sgpr_lo16 register when a
trunc/sext i16/i32 is generated, or a salu32 is used by vgpr16 or vice
versa. And this causes a problem as sgpr_lo16 is not fully supported in
the pipeline.

True16 mode works fine in -O3 mode since folding pass remove sgpr_lo16
from the pipeline. However it hit a problem in -O0 mode as folding pass
is skipped.

This patch did:
1. stop emitting sgpr_lo16 from isel
2. update codegen pattern to split uniformed/divergent pattern for
i16/i32 conversion
3. update fix-sgpr-copy pass to address legalization requirement in
true16 mode, update fix-sgpr-copies-f16-true16.mir
test to include all possible combinations

This patch is tested with cts and downstream repo with -O0 testing</pre>
</div>
</content>
</entry>
</feed>
