llvm-project.git/llvm/lib/Target/AMDGPU/SIDefines.h, branch users/mingmingl-llvm/samplefdo-profile-format

[AMDGPU] Add MSG_RTN_GET_CLUSTER_BARRIER_STATE (#157549)

2025-09-08T23:22:43+00:00

[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)

2025-09-03T23:25:18+00:00

This is a baseline support, it is not useable yet.

AMDGPU: Fold 64-bit immediate into copy to AV class (#155615)

2025-09-03T00:29:59+00:00

This is in preparation for patches which will intoduce more
copies to av registers.

[AMDGPU] Definitions of new gfx1250 HW_REG_MODE fields. NFC. (#156527)

2025-09-02T21:14:52+00:00

AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)

2025-08-20T13:54:37+00:00

64-bit version of 7425af4b7aaa31da10bd1bc7996d3bb212c79d88. We
still need to lower to 32-bit v_accagpr_write_b32s, so this has
a unique value restriction that requires both halves of the constant
to be 32-bit inline immediates. This only introduces the new
pseudo definitions, but doesn't try to use them yet.

[AMDGPU] Add NV bit to CPol::ALL mask. NFCI. (#153487)

2025-08-14T06:02:50+00:00

[AMDGPU] Fix the comment for OperandType. NFC. (#153489)

2025-08-14T06:02:28+00:00

[AMDGPU] Add MSG_SAVEWAVE_HAS_TDM on gfx1250 (#153483)

2025-08-14T06:01:50+00:00

[AMDGPU] Add HW_REG_IB_STS2 on gfx1250 (#153479)

2025-08-14T06:01:28+00:00

[AMDGPU] Add XNACK_STATE_PRIV and _MASK gfx1250 registers (#152374)

2025-08-06T21:44:17+00:00

Co-authored-by: Pierre Vanhoutryve 

Co-authored-by: Pierre Vanhoutryve