llvm-project.git/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h, branch users/mingmingl-llvm/samplefdo-profile-format Unnamed repository; edit this file 'description' to name the repository. [AMDGPU] Print high vgpr operand comments from objdump (#156966) 2025-09-04T23:56:49+00:00 Stanislav Mekhanoshin Stanislav.Mekhanoshin@amd.com 2025-09-04T23:56:49+00:00 a5f6db4b0d3d576f4ba9bd80d9cdf0b74cec8aa0 This followed the agreed convention: every basic block shall start with all MSBs zero. Codegen does the same lowering. 
This followed the agreed convention: every basic block shall
start with all MSBs zero. Codegen does the same lowering.
 [TableGen] Emit OpName as an enum class instead of a namespace (#125313) 2025-02-12T16:19:30+00:00 Rahul Joshi rjoshi@nvidia.com 2025-02-12T16:19:30+00:00 bee9664970d51df3f4e1d298d1bcb95bba364e17 - Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between values that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES. - Emit declaration of getOperandIdx() along with the OpName enum so it doesn't have to be repeated in various headers. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes). 
- Change InstrInfoEmitter to emit OpName as an enum class
  instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are 
  OpNames vs just operand indices and should help avoid
  bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
  enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
  to conform to the new definition of OpName (mostly
  mechanical changes).
 [AMDGPU] Include `<cstdint>` in AMDGPUMCTargetDesc (#101766) 2024-08-03T05:36:43+00:00 Sam James sam@gentoo.org 2024-08-03T05:36:43+00:00 8f39502b85d34998752193e85f36c408d3c99248 






[AMDGPU] Add an asm directive to track code_object_version (#76267)
2024-01-21T16:54:47+00:00

Emma Pilkington
emma.pilkington95@gmail.com

2024-01-21T16:54:47+00:00

bc82cfb38d83f1afeb2c290aa472c2e2e88919cb

Named '.amdhsa_code_object_version'. This directive sets the
e_ident[ABIVERSION] in the ELF header, and should be used as the assumed
COV for the rest of the asm file.

This commit also weakens the --amdhsa-code-object-version CL flag.
Previously, the CL flag took precedence over the IR flag. Now the IR
flag/asm directive take precedence over the CL flag. This is implemented
by merging a few COV-checking functions in AMDGPUBaseInfo.h.





Named '.amdhsa_code_object_version'. This directive sets the
e_ident[ABIVERSION] in the ELF header, and should be used as the assumed
COV for the rest of the asm file.

This commit also weakens the --amdhsa-code-object-version CL flag.
Previously, the CL flag took precedence over the IR flag. Now the IR
flag/asm directive take precedence over the CL flag. This is implemented
by merging a few COV-checking functions in AMDGPUBaseInfo.h.







[AMDGPU] Eliminate SIMCCodeEmitter and de-virtualise encoding methods.
2023-07-05T09:13:33+00:00

Ivan Kosarev
ivan.kosarev@amd.com

2023-07-05T09:07:43+00:00

ee165cdb1b8b5dad0c694f751e417968fca032fa

Simplifies some future changes needed for
<https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154337





Simplifies some future changes needed for
<https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154337







[CodeGen] Move instruction predicate verification to emitInstruction
2022-07-14T08:33:28+00:00

David Green
david.green@arm.com

2022-07-14T08:33:28+00:00

3e0bf1c7a9a4df5880f7a2c2d987c61b78fb499d

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo.  The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Recommitted with some fixes for the leftover MCII variables in release
builds.

Differential Revision: https://reviews.llvm.org/D129506





D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo.  The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Recommitted with some fixes for the leftover MCII variables in release
builds.

Differential Revision: https://reviews.llvm.org/D129506







Revert "Move instruction predicate verification to emitInstruction"
2022-07-13T12:28:11+00:00

David Green
david.green@arm.com

2022-07-13T12:28:11+00:00

95252133e125f36f5ce78192525ea23554fb5901

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are giving more warning
than I saw locally. Reverting to fix those issues.





This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are giving more warning
than I saw locally. Reverting to fix those issues.







Move instruction predicate verification to emitInstruction
2022-07-13T11:53:32+00:00

David Green
david.green@arm.com

2022-07-13T11:53:32+00:00

e2fb8c0f4b940e0285ee36c112469fa75d4b60ff

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo.  The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Differential Revision: https://reviews.llvm.org/D129506





D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo.  The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Differential Revision: https://reviews.llvm.org/D129506







[NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`
2022-02-16T05:10:09+00:00

Shao-Ce SUN
shaoce@nj.iscas.ac.cn

2022-02-16T05:09:59+00:00

2aed07e96c7a4f777e854fec619842c4289f8fbd

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D119846





Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D119846







[AMDGPU] Do not define GET_INSTRINFO_SCHED_ENUM
2022-02-15T21:00:54+00:00

Stanislav Mekhanoshin
Stanislav.Mekhanoshin@amd.com

2022-02-15T19:17:13+00:00

29a0e0a9e54f3863dd01a17552d4eda3c926b7f5

Autogenerated names are too long and break compilation on Windows,
while we do not need this enum at all.

Differential Revision: https://reviews.llvm.org/D119869





Autogenerated names are too long and break compilation on Windows,
while we do not need this enum at all.

Differential Revision: https://reviews.llvm.org/D119869