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<title>llvm-project.git/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AMDGPU] Add `GCNRPTarget` to track register pressure against a target  (#145765)</title>
<updated>2025-06-26T11:11:20+00:00</updated>
<author>
<name>Lucas Ramirez</name>
<email>11032120+lucas-rami@users.noreply.github.com</email>
</author>
<published>2025-06-26T11:11:20+00:00</published>
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<id>6307b496f8ba35e8921522d60cc1c9b5e1f6d899</id>
<content type='text'>
This adds the `GCNRPTarget` class which models a register pressure
target (i.e., maximum number of SGPRs/VGPRS) that one can track register
savings against. The only current use of this class is in the
scheduler's rematerialization stage. It replaces the more ad-hoc (and
now deleted) `ExcessRP` class which used to serve the same purpose.

This is only NFC~ish because `GCNRPTarget` tracks VGPR usage more
accurately than `ExcessRP` used to. To estimate required combined VGPR
savings we now additionally take into account the number of available
VGPRs in both banks (ArchVGPR and AGPR) at the time where the RP target
is created, whereas we used to only consider explicit savings made from
the starting RP. This makes VGPR savings estimations more accurate in
cases where we allow for savings in one VGPR bank to help towards
reducing pressure in another VGPR bank (see
`GCNRPTarget::CombineVGPRSavings`). This is the cause for unit test
changes.</content>
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<pre>
This adds the `GCNRPTarget` class which models a register pressure
target (i.e., maximum number of SGPRs/VGPRS) that one can track register
savings against. The only current use of this class is in the
scheduler's rematerialization stage. It replaces the more ad-hoc (and
now deleted) `ExcessRP` class which used to serve the same purpose.

This is only NFC~ish because `GCNRPTarget` tracks VGPR usage more
accurately than `ExcessRP` used to. To estimate required combined VGPR
savings we now additionally take into account the number of available
VGPRs in both banks (ArchVGPR and AGPR) at the time where the RP target
is created, whereas we used to only consider explicit savings made from
the starting RP. This makes VGPR savings estimations more accurate in
cases where we allow for savings in one VGPR bank to help towards
reducing pressure in another VGPR bank (see
`GCNRPTarget::CombineVGPRSavings`). This is the cause for unit test
changes.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)</title>
<updated>2025-06-24T09:09:36+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2025-06-24T09:09:36+00:00</published>
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<id>a201f8872a63aa336e4f79a40e196b6c20c9001e</id>
<content type='text'>
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.</content>
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<pre>
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Fix a potential integer overflow in GCNRegPressure when true16 is enabled (#144968)</title>
<updated>2025-06-20T16:29:32+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-06-20T16:29:32+00:00</published>
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<id>edbaf19c46c678e080d5a43e719bc19a02b44ca9</id>
<content type='text'>
Fixes SWDEV-537014.</content>
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<pre>
Fixes SWDEV-537014.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Simplify `GCNRegPressure::RegKind` (NFC) (#142682)</title>
<updated>2025-06-04T09:23:57+00:00</updated>
<author>
<name>Lucas Ramirez</name>
<email>11032120+lucas-rami@users.noreply.github.com</email>
</author>
<published>2025-06-04T09:23:57+00:00</published>
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<id>1f20cb9829240586ea215c4681f6f402ecccbb63</id>
<content type='text'>
This NFC simplifies the `GCNRegPressure::RegKind` enum so that instead
of containing a pair of values for each type of register (one for
non-tuple registers and one for tuple registers of that type) it only
contains one value representing all registers of that type.

The `GCNRegPressure::Value` array is still sized as before, though all
elements corresponding to tuple-kinds now start after all elements
corresponding to non-tuple-kinds instead of the two being interleaved.
This allows to simplify the `GCNRegPressure::inc` logic, eliminating the
switch entirely.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This NFC simplifies the `GCNRegPressure::RegKind` enum so that instead
of containing a pair of values for each type of register (one for
non-tuple registers and one for tuple registers of that type) it only
contains one value representing all registers of that type.

The `GCNRegPressure::Value` array is still sized as before, though all
elements corresponding to tuple-kinds now start after all elements
corresponding to non-tuple-kinds instead of the two being interleaved.
This allows to simplify the `GCNRegPressure::inc` logic, eliminating the
switch entirely.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Avoid repeated hash lookups (NFC) (#132511)</title>
<updated>2025-03-22T05:15:40+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-03-22T05:15:40+00:00</published>
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<id>f459cfed7b017ab57b8e825fc0198f89288168a4</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)</title>
<updated>2025-01-22T17:11:22+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-22T17:11:22+00:00</published>
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<id>9e6494c0fb29dfb5d4d2b7bf3ed7af261efee034</id>
<content type='text'>
This holds a physical register unit or virtual register and mask.

While I was here I've used emplace_back and removed an unneeded use of a
template.</content>
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<pre>
This holds a physical register unit or virtual register and mask.

While I was here I've used emplace_back and removed an unneeded use of a
template.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)</title>
<updated>2024-10-09T16:54:11+00:00</updated>
<author>
<name>Jeffrey Byrnes</name>
<email>jeffrey.byrnes@amd.com</email>
</author>
<published>2024-10-09T16:54:11+00:00</published>
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<id>17bc959961aa5792821516b547100316fc886ab4</id>
<content type='text'>
This adds the ability to use the GCNRPTrackers during scheduling. These trackers have several advantages over the generic trackers: 1. global live-thru trackers, 2. subregister based RP deltas, and 3. flexible vreg -&gt; PressureSet mappings.

This feature is off-by-default to ease with the roll-out process. In particular, when using the optional trackers, the scheduler will still maintain the generic trackers leading to unnecessary compile time.
</content>
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<pre>
This adds the ability to use the GCNRPTrackers during scheduling. These trackers have several advantages over the generic trackers: 1. global live-thru trackers, 2. subregister based RP deltas, and 3. flexible vreg -&gt; PressureSet mappings.

This feature is off-by-default to ease with the roll-out process. In particular, when using the optional trackers, the scheduler will still maintain the generic trackers leading to unnecessary compile time.
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Constrain use LiveMask by the operand's LaneMask for RP calculation.</title>
<updated>2024-10-08T17:29:50+00:00</updated>
<author>
<name>Jeffrey Byrnes</name>
<email>Jeffrey.Byrnes@amd.com</email>
</author>
<published>2024-10-07T18:55:13+00:00</published>
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<id>5cb6b15568c1554a2ea89fee849ed0e27b785ee0</id>
<content type='text'>
For speculative RP queries, recede may calculate inaccurate masks for subreg uses. Previously, the calculation would look at any live lane for the use at the position of the MI in the LIS. This also adds lanes for any subregs which are live at but not used by the instruction. By constraining against the getSubRegIndexLaneMask for the operand's subreg, we are sure to not pick up on these extra lanes.

For current clients of recede, this is not an issue. This is because 1. the current clients do not violate the program order in the LIS, and 2. the change to RP is based on the difference between previous mask and new mask. Since current clients are not exposed to this issue, this patch is sort of NFC.

Co-authored-by: Valery Pykhtin Valery.Pykhtin@amd.com
Change-Id: Iaed80271226b2587297e6fb78fe081afec1a9275
</content>
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<pre>
For speculative RP queries, recede may calculate inaccurate masks for subreg uses. Previously, the calculation would look at any live lane for the use at the position of the MI in the LIS. This also adds lanes for any subregs which are live at but not used by the instruction. By constraining against the getSubRegIndexLaneMask for the operand's subreg, we are sure to not pick up on these extra lanes.

For current clients of recede, this is not an issue. This is because 1. the current clients do not violate the program order in the LIS, and 2. the change to RP is based on the difference between previous mask and new mask. Since current clients are not exposed to this issue, this patch is sort of NFC.

Co-authored-by: Valery Pykhtin Valery.Pykhtin@amd.com
Change-Id: Iaed80271226b2587297e6fb78fe081afec1a9275
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Qualify auto. NFC. (#110878)</title>
<updated>2024-10-03T12:07:54+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-10-03T12:07:54+00:00</published>
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<id>8d13e7b8c382499c1cf0c2a3184b483e760f266b</id>
<content type='text'>
Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)</content>
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<pre>
Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)</title>
<updated>2024-07-10T11:34:48+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2024-07-10T11:34:48+00:00</published>
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<id>abde52aa667118d18e9551ab87a15b95c267b3b6</id>
<content type='text'>
- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.</content>
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<pre>
- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.</pre>
</div>
</content>
</entry>
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