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<title>llvm-project.git/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp, branch users/mingmingl-llvm/samplefdo-profile-format</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>AMDGPU: Avoid directly using MCOperandInfo RegClass field (#156641)</title>
<updated>2025-09-03T10:50:07+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-03T10:50:07+00:00</published>
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<id>a1bfa2f6a69b9bff45529809af932f0484795b90</id>
<content type='text'>
This value should not be directly interpreted. Also avoids
a function only used for an assert.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This value should not be directly interpreted. Also avoids
a function only used for an assert.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Fix a warning</title>
<updated>2025-09-02T16:25:16+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-09-02T16:25:16+00:00</published>
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<id>83f390859e186d22af8aa32135d7993079ed4666</id>
<content type='text'>
This patch fixes:

  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:298:9: error: unused
  variable 'Src0Idx' [-Werror,-Wunused-variable]
</content>
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<pre>
This patch fixes:

  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:298:9: error: unused
  variable 'Src0Idx' [-Werror,-Wunused-variable]
</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (#155595)</title>
<updated>2025-09-02T16:19:01+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-02T16:19:01+00:00</published>
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<id>bb54be585370cc281e60fb6973062004f200c9d3</id>
<content type='text'>
It is not safe to use isOperandLegal on an instruction that does
not have a complete set of operands. Unforunately the APIs are
not set up in a convenient way to speculatively check if an instruction
will be legal in a hypothetical instruction. Build all the operands
and then verify they are legal after. This is clumsy, we should have
a more direct check for will these operands give a legal instruction.

This seems to fix a missed optimization in the gfx11 test. The
fold was firing for gfx1150, but not gfx1100. Both should support
vop3 literals so I'm not sure why it wasn't working before.</content>
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<pre>
It is not safe to use isOperandLegal on an instruction that does
not have a complete set of operands. Unforunately the APIs are
not set up in a convenient way to speculatively check if an instruction
will be legal in a hypothetical instruction. Build all the operands
and then verify they are legal after. This is clumsy, we should have
a more direct check for will these operands give a legal instruction.

This seems to fix a missed optimization in the gfx11 test. The
fold was firing for gfx1150, but not gfx1100. Both should support
vop3 literals so I'm not sure why it wasn't working before.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Per-subtarget DPP instruction classification (#153096)</title>
<updated>2025-08-11T22:41:02+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-11T22:41:02+00:00</published>
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<id>ea14834966ad666856246f24de46397cbfc932eb</id>
<content type='text'>
This is NFCI at this point.</content>
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<pre>
This is NFCI at this point.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Fix DPP combining into V_BITOP3_B32 (#153083)</title>
<updated>2025-08-11T22:39:02+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-11T22:39:02+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)</title>
<updated>2025-05-23T15:30:29+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-23T15:30:29+00:00</published>
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<id>52c2e45c11ee37d8efcf87cbfa5c9f23cbdd566b</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Construct SmallVector with iterator ranges (NFC) (#136415)</title>
<updated>2025-04-19T16:09:41+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-19T16:09:41+00:00</published>
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<id>e7c07a021034c7469c3c4a6f65299152291091ed</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918)</title>
<updated>2025-03-31T14:18:25+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-03-31T14:18:25+00:00</published>
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<id>a61cc1b99a50d832c650132cc9956320bfe594f5</id>
<content type='text'>
We only emits v_mov_b32/64_dpp. Don't combine t16 instructions with mov
dpp. Update the test inputs to be legal.

It is future work to emit v_mov_b16_dpp, and then update GCNDPPCombine
to combine it with the 16-bit instructions.</content>
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<pre>
We only emits v_mov_b32/64_dpp. Don't combine t16 instructions with mov
dpp. Update the test inputs to be legal.

It is future work to emit v_mov_b16_dpp, and then update GCNDPPCombine
to combine it with the 16-bit instructions.</pre>
</div>
</content>
</entry>
<entry>
<title>[TableGen] Emit OpName as an enum class instead of a namespace (#125313)</title>
<updated>2025-02-12T16:19:30+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-02-12T16:19:30+00:00</published>
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<id>bee9664970d51df3f4e1d298d1bcb95bba364e17</id>
<content type='text'>
- Change InstrInfoEmitter to emit OpName as an enum class
  instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are 
  OpNames vs just operand indices and should help avoid
  bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
  enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
  to conform to the new definition of OpName (mostly
  mechanical changes).</content>
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<pre>
- Change InstrInfoEmitter to emit OpName as an enum class
  instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are 
  OpNames vs just operand indices and should help avoid
  bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
  enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
  to conform to the new definition of OpName (mostly
  mechanical changes).</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Qualify auto. NFC. (#110878)</title>
<updated>2024-10-03T12:07:54+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-10-03T12:07:54+00:00</published>
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<id>8d13e7b8c382499c1cf0c2a3184b483e760f266b</id>
<content type='text'>
Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)</content>
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<pre>
Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)</pre>
</div>
</content>
</entry>
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