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<title>llvm-project.git/llvm/lib/Target/AMDGPU/EXPInstructions.td, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>AMDGPU: Remove export and related instructions from gfx1250 support (#145624)</title>
<updated>2025-06-25T02:59:26+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-06-25T02:59:26+00:00</published>
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<pre>
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<entry>
<title>[AMDGPU] Remove unnecessary predicates from aliases. NFC. (#91602)</title>
<updated>2024-05-10T14:04:38+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-05-10T14:04:38+00:00</published>
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So long as the target of the alias is predicated with HasImageInsts or
similar, the alias itself does not need this predicate.</content>
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So long as the target of the alias is predicated with HasImageInsts or
similar, the alias itself does not need this predicate.</pre>
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<entry>
<title>[AMDGPU] Create AMDGPUMnemonicAlias tablegen class (#89288)</title>
<updated>2024-05-09T15:37:56+00:00</updated>
<author>
<name>Joe Nash</name>
<email>joseph.nash@amd.com</email>
</author>
<published>2024-05-09T15:37:56+00:00</published>
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<content type='text'>
AMDGPUMnemonicAlias is a MnemonicAlias that inherits from
GCNPredicateControl, so that we can set predicates on the alias the same
way as Instructions.
Use AssemblerPredicate instead of Requires on aliases

NFC.</content>
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AMDGPUMnemonicAlias is a MnemonicAlias that inherits from
GCNPredicateControl, so that we can set predicates on the alias the same
way as Instructions.
Use AssemblerPredicate instead of Requires on aliases

NFC.</pre>
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</entry>
<entry>
<title>[AMDGPU] Simplify EXP Real instruction definitions. NFC.</title>
<updated>2024-03-07T11:04:43+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-03-07T10:58:33+00:00</published>
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Pass the Pseudo (instead of its name) into EXP_Real_Row and
EXP_Real_ComprVM since it is already available in all subclasses.
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<pre>
Pass the Pseudo (instead of its name) into EXP_Real_Row and
EXP_Real_ComprVM since it is already available in all subclasses.
</pre>
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</entry>
<entry>
<title>AMDGPI: Rename HasExpOrExportInsts to HasExportInsts. NFC (#84252)</title>
<updated>2024-03-06T22:59:28+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2024-03-06T22:59:28+00:00</published>
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<entry>
<title>AMDGPU: Define HasExpOrExportInsts for export instruction definitions. (#84083)</title>
<updated>2024-03-05T23:32:32+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2024-03-05T23:32:32+00:00</published>
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<pre>
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</entry>
<entry>
<title>[AMDGPU] Refactor export instruction definitions. NFC. (#81738)</title>
<updated>2024-02-14T15:10:04+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-02-14T15:10:04+00:00</published>
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<content type='text'>
Using multiclasses for the Real instruction definitions has a couple of
benefits:
- It avoids repeating information that was already specified when
  defining the corresponding pseudo, like the row and done bits.
- It allows commoning up the Real definitions for architectures which
  are mostly the same, like GFX11 and GFX12.</content>
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<pre>
Using multiclasses for the Real instruction definitions has a couple of
benefits:
- It avoids repeating information that was already specified when
  defining the corresponding pseudo, like the row and done bits.
- It allows commoning up the Real definitions for architectures which
  are mostly the same, like GFX11 and GFX12.</pre>
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</entry>
<entry>
<title>[AMDGPU] Flip the default value of maybeAtomic. NFCI. (#75220)</title>
<updated>2024-01-09T10:20:32+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-01-09T10:20:32+00:00</published>
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<content type='text'>
In practice maybeAtomic = 0 is used to prevent SIMemoryLegalizer from
interfering with instructions that are mayLoad or mayStore but lack
MachineMemOperands. These instructions should be the exception not the
rule, so this patch sets maybeAtomic = 1 by default and only overrides
it to 0 where necessary.</content>
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In practice maybeAtomic = 0 is used to prevent SIMemoryLegalizer from
interfering with instructions that are mayLoad or mayStore but lack
MachineMemOperands. These instructions should be the exception not the
rule, so this patch sets maybeAtomic = 1 by default and only overrides
it to 0 where necessary.</pre>
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</entry>
<entry>
<title>[AMDGPU] Add VEXPORT encoding for GFX12 (#74615)</title>
<updated>2023-12-07T10:06:20+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-12-07T10:06:20+00:00</published>
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<content type='text'>
In GFX12 the exp instruction is renamed to export, but exp is still
accepted as an alias.

Co-authored-by: Mateja Marjanovic &lt;mateja.marjanovic@amd.com&gt;</content>
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<pre>
In GFX12 the exp instruction is renamed to export, but exp is still
accepted as an alias.

Co-authored-by: Mateja Marjanovic &lt;mateja.marjanovic@amd.com&gt;</pre>
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</entry>
<entry>
<title>[AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row</title>
<updated>2022-06-16T17:23:14+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2022-06-13T17:20:52+00:00</published>
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<content type='text'>
Differential Revision: https://reviews.llvm.org/D127671
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Differential Revision: https://reviews.llvm.org/D127671
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