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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)</title>
<updated>2025-06-24T09:09:36+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2025-06-24T09:09:36+00:00</published>
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<id>a201f8872a63aa336e4f79a40e196b6c20c9001e</id>
<content type='text'>
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Remove legacy PM version of AMDGPUPromoteAllocaToVector (#144986)</title>
<updated>2025-06-20T07:43:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-20T07:43:39+00:00</published>
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<id>1cae21da47b1f53c3946534b12507a035fb283d2</id>
<content type='text'>
This is only run in the middle end with the new pass manager now,
so garbage collect the old PM version.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is only run in the middle end with the new pass manager now,
so garbage collect the old PM version.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[AMDGPU] Extended vector promotion to aggregate types." (#144366)</title>
<updated>2025-06-16T15:06:18+00:00</updated>
<author>
<name>zGoldthorpe</name>
<email>Zach.Goldthorpe@amd.com</email>
</author>
<published>2025-06-16T15:06:18+00:00</published>
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<id>4692f0d3448e32381a2b21c7359c7daed07a8850</id>
<content type='text'>
Reverts llvm/llvm-project#143784

Patch fails some internal tests. Will investigate more thoroughly before
attempting to remerge.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Reverts llvm/llvm-project#143784

Patch fails some internal tests. Will investigate more thoroughly before
attempting to remerge.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Extended vector promotion to aggregate types. (#143784)</title>
<updated>2025-06-13T18:22:21+00:00</updated>
<author>
<name>zGoldthorpe</name>
<email>Zach.Goldthorpe@amd.com</email>
</author>
<published>2025-06-13T18:22:21+00:00</published>
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<id>79e06bf1ae9961c5045134288fd8acc9173f6be2</id>
<content type='text'>
Extends the `amdgpu-promote-alloca-to-vector` pass to also promote
aggregate types whose elements are all the same type to vector
registers.

The motivation for this extension was to account for IR generated by the
frontend containing several singleton struct types containing vectors or
vector-like elements, though the implementation is strictly more
general.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Extends the `amdgpu-promote-alloca-to-vector` pass to also promote
aggregate types whose elements are all the same type to vector
registers.

The motivation for this extension was to account for IR generated by the
frontend containing several singleton struct types containing vectors or
vector-like elements, though the implementation is strictly more
general.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Promote nestedGEP allocas to vectors (#141199)</title>
<updated>2025-06-02T08:20:14+00:00</updated>
<author>
<name>Harrison Hao</name>
<email>57025411+harrisonGPU@users.noreply.github.com</email>
</author>
<published>2025-06-02T08:20:14+00:00</published>
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<id>1a7f5f58332d91f88a4305399d7f79aba046e19a</id>
<content type='text'>
Supports the `nestedGEP`pattern that
 appears when an alloca is first indexed as an array element and then
 shifted with a byte‑offset GEP:

```llvm
  %SortedFragments = alloca [10 x &lt;2 x i32&gt;], addrspace(5), align 8
  %row  = getelementptr [10 x &lt;2 x i32&gt;], ptr addrspace(5) %SortedFragments, i32 0, i32 %j
  %elt1 = getelementptr i8, ptr addrspace(5) %row, i32 4
  %val  = load i32, ptr addrspace(5) %elt1
```

The pass folds the two levels of addressing into a single vector lane
 index and keeps the whole object in a VGPR:

```llvm
  %vec  = freeze &lt;20 x i32&gt; poison              ; alloca promote  &lt;20 x i32&gt;
  %idx0 = mul i32 %j, 2                         ; j * 2
  %idx  = add i32 %idx0, 1                      ; j * 2 + 1
  %val  = extractelement &lt;20 x i32&gt; %vec, i32 %idx
```

This eliminates the scratch read.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Supports the `nestedGEP`pattern that
 appears when an alloca is first indexed as an array element and then
 shifted with a byte‑offset GEP:

```llvm
  %SortedFragments = alloca [10 x &lt;2 x i32&gt;], addrspace(5), align 8
  %row  = getelementptr [10 x &lt;2 x i32&gt;], ptr addrspace(5) %SortedFragments, i32 0, i32 %j
  %elt1 = getelementptr i8, ptr addrspace(5) %row, i32 4
  %val  = load i32, ptr addrspace(5) %elt1
```

The pass folds the two levels of addressing into a single vector lane
 index and keeps the whole object in a VGPR:

```llvm
  %vec  = freeze &lt;20 x i32&gt; poison              ; alloca promote  &lt;20 x i32&gt;
  %idx0 = mul i32 %j, 2                         ; j * 2
  %idx  = add i32 %idx0, 1                      ; j * 2 + 1
  %val  = extractelement &lt;20 x i32&gt; %vec, i32 %idx
```

This eliminates the scratch read.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] PromoteAlloca: handle out-of-bounds GEP for shufflevector (#139700)</title>
<updated>2025-05-21T13:28:30+00:00</updated>
<author>
<name>Robert Imschweiler</name>
<email>robert.imschweiler@amd.com</email>
</author>
<published>2025-05-21T13:28:30+00:00</published>
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<id>dc29901efb18880679b965538ae8bc3f6dd5ecd8</id>
<content type='text'>
This LLVM defect was identified via the AMD Fuzzing project.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This LLVM defect was identified via the AMD Fuzzing project.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Max. WG size-induced occupancy limits max. waves/EU (#137807)</title>
<updated>2025-05-01T11:22:23+00:00</updated>
<author>
<name>Lucas Ramirez</name>
<email>11032120+lucas-rami@users.noreply.github.com</email>
</author>
<published>2025-05-01T11:22:23+00:00</published>
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<id>e377dc4d38b69050a3301c68637d1b6dacaee3a9</id>
<content type='text'>
The default maximum waves/EU returned by the family of
`AMDGPUSubtarget::getWavesPerEU` is currently the maximum number of
waves/EU supported by the subtarget (only a valid occupancy range in
"amdgpu-waves-per-eu" may lower that maximum). This ignores maximum
achievable occupancy imposed by flat workgroup size and LDS usage,
resulting in situations where `AMDGPUSubtarget::getWavesPerEU` produces
a maximum higher than the one from
`AMDGPUSubtarget::getOccupancyWithWorkGroupSizes`.

This limits the waves/EU range's maximum to the maximum achievable
occupancy derived from flat workgroup sizes and LDS usage. This only has
an impact on functions which restrict flat workgroup size with
"amdgpu-flat-work-group-size", since the default range of flat workgroup
sizes achieves the maximum number of waves/EU supported by the
subtarget.

Improvements to the handling of "amdgpu-waves-per-eu" are left for a
follow up PR (e.g., I think the attribute should be able to lower the
full range of waves/EU produced by these methods).</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The default maximum waves/EU returned by the family of
`AMDGPUSubtarget::getWavesPerEU` is currently the maximum number of
waves/EU supported by the subtarget (only a valid occupancy range in
"amdgpu-waves-per-eu" may lower that maximum). This ignores maximum
achievable occupancy imposed by flat workgroup size and LDS usage,
resulting in situations where `AMDGPUSubtarget::getWavesPerEU` produces
a maximum higher than the one from
`AMDGPUSubtarget::getOccupancyWithWorkGroupSizes`.

This limits the waves/EU range's maximum to the maximum achievable
occupancy derived from flat workgroup sizes and LDS usage. This only has
an impact on functions which restrict flat workgroup size with
"amdgpu-flat-work-group-size", since the default range of flat workgroup
sizes achieves the maximum number of waves/EU supported by the
subtarget.

Improvements to the handling of "amdgpu-waves-per-eu" are left for a
follow up PR (e.g., I think the attribute should be able to lower the
full range of waves/EU produced by these methods).</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Avoid crashes for non-byte-sized types in PromoteAlloca (#134042)</title>
<updated>2025-04-14T07:13:54+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-04-14T07:13:54+00:00</published>
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<id>cf188d650ce26b4ee3e11101d844361fca15ba64</id>
<content type='text'>
This patch addresses three problems when promoting allocas to vectors:
- Element types with size &lt; 1 byte in allocas with a vector type caused
  divisions by zero.
- Element types whose size doesn't match their AllocSize hit an assertion.
- Access types whose size doesn't match their AllocSize hit an assertion.

With this patch, we do not attempt to promote affected allocas to vectors. In
principle, we could handle these cases in PromoteAlloca, e.g., by truncating
and extending elements from/to their allocation size. It's however unclear if
we ever encounter such cases in practice, so that doesn't seem worth the added
complexity.

For SWDEV-511252</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch addresses three problems when promoting allocas to vectors:
- Element types with size &lt; 1 byte in allocas with a vector type caused
  divisions by zero.
- Element types whose size doesn't match their AllocSize hit an assertion.
- Access types whose size doesn't match their AllocSize hit an assertion.

With this patch, we do not attempt to promote affected allocas to vectors. In
principle, we could handle these cases in PromoteAlloca, e.g., by truncating
and extending elements from/to their allocation size. It's however unclear if
we ever encounter such cases in practice, so that doesn't seem worth the added
complexity.

For SWDEV-511252</pre>
</div>
</content>
</entry>
<entry>
<title>[IRBuilder] Add new overload for CreateIntrinsic (#131942)</title>
<updated>2025-03-31T15:10:34+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-03-31T15:10:34+00:00</published>
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<id>74b7abf15452574808834c0a08dd2af6bada2648</id>
<content type='text'>
Add a new `CreateIntrinsic` overload with no `Types`, useful for
creating calls to non-overloaded intrinsics that don't need additional
mangling.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a new `CreateIntrinsic` overload with no `Types`, useful for
creating calls to non-overloaded intrinsics that don't need additional
mangling.</pre>
</div>
</content>
</entry>
<entry>
<title>[Target] Use *Set::insert_range (NFC) (#132140)</title>
<updated>2025-03-20T16:09:30+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-03-20T16:09:30+00:00</published>
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<id>71935281e02cfaef2bd109bcb58f0d80039ffd15</id>
<content type='text'>
DenseSet, SmallPtrSet, SmallSet, SetVector, and StringSet recently
gained C++23-style insert_range.  This patch replaces:

  Dest.insert(Src.begin(), Src.end());

with:

  Dest.insert_range(Src);

This patch does not touch custom begin like succ_begin for now.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
DenseSet, SmallPtrSet, SmallSet, SetVector, and StringSet recently
gained C++23-style insert_range.  This patch replaces:

  Dest.insert(Src.begin(), Src.end());

with:

  Dest.insert_range(Src);

This patch does not touch custom begin like succ_begin for now.</pre>
</div>
</content>
</entry>
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