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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU] upstream barrier count reporting part1 (#154409)</title>
<updated>2025-08-19T23:42:31+00:00</updated>
<author>
<name>Gang Chen</name>
<email>gangc@amd.com</email>
</author>
<published>2025-08-19T23:42:31+00:00</published>
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<pre>
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</entry>
<entry>
<title>Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)</title>
<updated>2024-09-13T09:54:30+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2024-09-13T09:54:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=335620853117153e52ce54fe4e879f66aa23ff99'/>
<id>335620853117153e52ce54fe4e879f66aa23ff99</id>
<content type='text'>
This reverts commit
https://github.com/llvm/llvm-project/commit/7792b4ae79e5ac9355ee13b01f16e25455f8427f.

The problem was a conflict with
https://github.com/llvm/llvm-project/commit/e55d6f5ea2656bf842973d8bee86c3ace31bc865
"[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive
(https://github.com/llvm/llvm-project/pull/107889)"
which changed the syntax of V_SET_INACTIVE (and thus made my MIR test
crash).

...if only we had a merge queue.</content>
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<pre>
This reverts commit
https://github.com/llvm/llvm-project/commit/7792b4ae79e5ac9355ee13b01f16e25455f8427f.

The problem was a conflict with
https://github.com/llvm/llvm-project/commit/e55d6f5ea2656bf842973d8bee86c3ace31bc865
"[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive
(https://github.com/llvm/llvm-project/pull/107889)"
which changed the syntax of V_SET_INACTIVE (and thus made my MIR test
crash).

...if only we had a merge queue.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)"" (#108341)</title>
<updated>2024-09-12T08:12:09+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2024-09-12T08:12:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7792b4ae79e5ac9355ee13b01f16e25455f8427f'/>
<id>7792b4ae79e5ac9355ee13b01f16e25455f8427f</id>
<content type='text'>
Reverts llvm/llvm-project#108173

si-init-whole-wave.mir crashes on some buildbots (although it passed
both locally with sanitizers enabled and in pre-merge tests).
Investigating.</content>
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Reverts llvm/llvm-project#108173

si-init-whole-wave.mir crashes on some buildbots (although it passed
both locally with sanitizers enabled and in pre-merge tests).
Investigating.</pre>
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</content>
</entry>
<entry>
<title>Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)" (#108173)</title>
<updated>2024-09-12T07:11:41+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2024-09-12T07:11:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=703ebca869e1e684147d316b7bdb15437c12206a'/>
<id>703ebca869e1e684147d316b7bdb15437c12206a</id>
<content type='text'>
This reverts commit
https://github.com/llvm/llvm-project/commit/c7a7767fca736d0447832ea4d4587fb3b9e797c2.

The buildbots failed because I removed a MI from its parent before
updating LIS. This PR should fix that.</content>
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<pre>
This reverts commit
https://github.com/llvm/llvm-project/commit/c7a7767fca736d0447832ea4d4587fb3b9e797c2.

The buildbots failed because I removed a MI from its parent before
updating LIS. This PR should fix that.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)</title>
<updated>2024-09-10T16:51:43+00:00</updated>
<author>
<name>Vitaly Buka</name>
<email>vitalybuka@google.com</email>
</author>
<published>2024-09-10T16:51:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c7a7767fca736d0447832ea4d4587fb3b9e797c2'/>
<id>c7a7767fca736d0447832ea4d4587fb3b9e797c2</id>
<content type='text'>
Breaks bots, see #105822.

Reverts llvm/llvm-project#105822</content>
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<pre>
Breaks bots, see #105822.

Reverts llvm/llvm-project#105822</pre>
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</entry>
<entry>
<title>[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic (#105822)</title>
<updated>2024-09-10T11:24:53+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2024-09-10T11:24:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=44556e64f21c1e21dd0e8329bc0e54e1887261c5'/>
<id>44556e64f21c1e21dd0e8329bc0e54e1887261c5</id>
<content type='text'>
This intrinsic is meant to be used in functions that have a "tail" that
needs to be run with all the lanes enabled. The "tail" may contain
complex control flow that makes it unsuitable for the use of the
existing WWM intrinsics. Instead, we will pretend that the function
starts with all the lanes enabled, then branches into the actual body of
the function for the lanes that were meant to run it, and then finally
all the lanes will rejoin and run the tail.

As such, the intrinsic will return the EXEC mask for the body of the
function, and is meant to be used only as part of a very limited pattern
(for now only in amdgpu_cs_chain functions):

```
entry:
  %func_exec = call i1 @llvm.amdgcn.init.whole.wave()
  br i1 %func_exec, label %func, label %tail

func:
  ; ... stuff that should run with the actual EXEC mask
  br label %tail

tail:
  ; ... stuff that runs with all the lanes enabled;
  ; can contain more than one basic block
```

It's an error to use the result of this intrinsic for anything
other than a branch (but unfortunately checking that in the verifier is
non-trivial because SIAnnotateControlFlow will introduce an amdgcn.if
between the intrinsic and the branch).

The intrinsic is lowered to a SI_INIT_WHOLE_WAVE pseudo, which for now
is expanded in si-wqm (which is where SI_INIT_EXEC is handled too);
however the information that the function was conceptually started in
whole wave mode is stored in the machine function info
(hasInitWholeWave). This will be useful in prolog epilog insertion,
where we can skip saving the inactive lanes for CSRs (since if the
function started with all the lanes active, then there are no inactive
lanes to preserve).</content>
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<pre>
This intrinsic is meant to be used in functions that have a "tail" that
needs to be run with all the lanes enabled. The "tail" may contain
complex control flow that makes it unsuitable for the use of the
existing WWM intrinsics. Instead, we will pretend that the function
starts with all the lanes enabled, then branches into the actual body of
the function for the lanes that were meant to run it, and then finally
all the lanes will rejoin and run the tail.

As such, the intrinsic will return the EXEC mask for the body of the
function, and is meant to be used only as part of a very limited pattern
(for now only in amdgpu_cs_chain functions):

```
entry:
  %func_exec = call i1 @llvm.amdgcn.init.whole.wave()
  br i1 %func_exec, label %func, label %tail

func:
  ; ... stuff that should run with the actual EXEC mask
  br label %tail

tail:
  ; ... stuff that runs with all the lanes enabled;
  ; can contain more than one basic block
```

It's an error to use the result of this intrinsic for anything
other than a branch (but unfortunately checking that in the verifier is
non-trivial because SIAnnotateControlFlow will introduce an amdgcn.if
between the intrinsic and the branch).

The intrinsic is lowered to a SI_INIT_WHOLE_WAVE pseudo, which for now
is expanded in si-wqm (which is where SI_INIT_EXEC is handled too);
however the information that the function was conceptually started in
whole wave mode is stored in the machine function info
(hasInitWholeWave). This will be useful in prolog epilog insertion,
where we can skip saving the inactive lanes for CSRs (since if the
function started with all the lanes active, then there are no inactive
lanes to preserve).</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)</title>
<updated>2024-01-04T13:35:12+00:00</updated>
<author>
<name>Chaitanya</name>
<email>Krishna.Sankisa@amd.com</email>
</author>
<published>2024-01-04T13:35:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9803de0e8e3abbbc94a4265d5847db435897a384'/>
<id>9803de0e8e3abbbc94a4265d5847db435897a384</id>
<content type='text'>
"hidden_dynamic_lds_size" argument will be added in the reserved section
at offset 120 of the implicit argument layout.
Add "isDynamicLDSUsed" flag to AMDGPUMachineFunction to identify if a
function uses dynamic LDS.

hidden argument will be added in below cases:

- LDS global is used in the kernel.
- Kernel calls a function which uses LDS global.
- LDS pointer is passed as argument to kernel itself.</content>
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<pre>
"hidden_dynamic_lds_size" argument will be added in the reserved section
at offset 120 of the implicit argument layout.
Add "isDynamicLDSUsed" flag to AMDGPUMachineFunction to identify if a
function uses dynamic LDS.

hidden argument will be added in below cases:

- LDS global is used in the kernel.
- Kernel calls a function which uses LDS global.
- LDS pointer is passed as argument to kernel itself.</pre>
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</content>
</entry>
<entry>
<title>[Target] Remove unused forward declarations (NFC)</title>
<updated>2023-12-10T18:38:55+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2023-12-10T18:38:55+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Introduce isBottomOfStack helper. NFC (#74288)</title>
<updated>2023-12-06T08:56:13+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2023-12-06T08:56:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=40d802a6b6d507c9ae9dc7b0462e54652b42ad39'/>
<id>40d802a6b6d507c9ae9dc7b0462e54652b42ad39</id>
<content type='text'>
Introduce a helper to check if a function is at the bottom of the stack,
i.e. if it's an entry function or a chain function.
This was suggested in #71913.</content>
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<pre>
Introduce a helper to check if a function is at the bottom of the stack,
i.e. if it's an entry function or a chain function.
This was suggested in #71913.</pre>
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</entry>
<entry>
<title>[AMDGPU] Add IsChainFunction to the MachineFunctionInfo</title>
<updated>2023-08-21T10:37:32+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2023-07-27T09:10:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=5272ae667dd5c628689097687f4679a8be29bc4d'/>
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<content type='text'>
This will represent functions with the amdgpu_cs_chain or
amdgpu_cs_chain_preserve calling conventions.

Differential Revision: https://reviews.llvm.org/D156410
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This will represent functions with the amdgpu_cs_chain or
amdgpu_cs_chain_preserve calling conventions.

Differential Revision: https://reviews.llvm.org/D156410
</pre>
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