llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp, branch users/fmayer/spr/main.flowsensitive-statusor-2n-add-minimal-model

[AMDGPU] Remove NoInfsFPMath uses (#163028)

2025-10-13T11:15:49+00:00

Only `ninf` should be used.

[AMDGPU] Add the support for 45-bit buffer resource (#159702)

2025-09-24T15:12:02+00:00

On new targets like `gfx1250`, the buffer resource (V#) now uses this
format:

```
base (57-bit): resource[56:0]
num_records (45-bit): resource[101:57]
reserved (6-bit): resource[107:102]
stride (14-bit): resource[121:108]
```

This PR changes the type of `num_records` from `i32` to `i64` in both
builtin and intrinsic, and also adds the support for lowering the new
format.

Fixes SWDEV-554034.

---------

Co-authored-by: Krzysztof Drewniak

[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754)

2025-09-16T09:26:32+00:00

[AMDGPU] Support lowering of cluster related instrinsics (#157978)

2025-09-13T01:11:17+00:00

Since many code are connected, this also changes how workgroup id is lowered.

Co-authored-by: Jay Foad 
Co-authored-by: Ivan Kosarev

[AMDGPU][Legalizer] Avoid pack/unpack for G_FSHR (#156796)

2025-09-04T23:12:57+00:00

Scalarize G_FSHR only if the subtarget does not support V2S16 type.

[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)

2025-09-04T09:19:25+00:00

- Add clang built-ins + sema/codegen
- Add IR Intrinsic + verifier
- Add DAG/GlobalISel codegen for the intrinsics
- Add lowering in SIMemoryLegalizer using a MMO flag.

[AMDGPU] Remove `ApproxFuncFPMath` uses (#155578)

2025-08-28T03:09:01+00:00

One of options in `resetTargetOptions`, this removes `ApproxFuncFPMath`
in AMDGPU part.

[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)

2025-08-18T15:04:27+00:00

Lowering in GlobalISel for AMDGPU previously always narrows to i32 on
truncating store regardless of mem size or scalar size, causing issues
with types like i65 which is first extended to i128 then stored as i64 +
i8 to i128 locations. Narrowing only on store to pow of 2 mem location
ensures only narrowing to mem size near end of legalization.

This LLVM defect was identified via the AMD Fuzzing project.

[AMDGPU] Per-subtarget DPP instruction classification (#153096)

2025-08-11T22:41:02+00:00

This is NFCI at this point.

[AMDGPU] Fix buffer addressing mode matching (#152584)

2025-08-07T21:23:41+00:00

Starting in gfx1250, voffset and immoffset are zero-extended from 32
bits
to 45 bits before being added together.