llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp, branch main Unnamed repository; edit this file 'description' to name the repository. [AMDGPU][GlobalISel] Lower G_FMINIMUM and G_FMAXIMUM (#151122) 2025-10-24T12:48:27+00:00 Mirko BrkuĊĦanin Mirko.Brkusanin@amd.com 2025-10-24T12:48:27+00:00 fe5f49942eb7b27989b04736bc91e14730dc478d Add GlobalISel lowering of G_FMINIMUM and G_FMAXIMUM following the same logic as in SDag's expandFMINIMUM_FMAXIMUM. Update AMDGPU legalization rules: Pre GFX12 now uses new lowering method and make G_FMINNUM_IEEE and G_FMAXNUM_IEEE legal to match SDag. 
Add GlobalISel lowering of G_FMINIMUM and G_FMAXIMUM following the same
logic as in SDag's expandFMINIMUM_FMAXIMUM.
Update AMDGPU legalization rules: Pre GFX12 now uses new lowering method
and make G_FMINNUM_IEEE and G_FMAXNUM_IEEE legal to match SDag.
 [AMDGPU] Remove NoInfsFPMath uses (#163028) 2025-10-13T11:15:49+00:00 paperchalice liujunchang97@outlook.com 2025-10-13T11:15:49+00:00 14a42e64cf2bd1e6dcc3bbc417d02cf773cb9752 Only `ninf` should be used. 
Only `ninf` should be used.
 [AMDGPU] Add the support for 45-bit buffer resource (#159702) 2025-09-24T15:12:02+00:00 Shilei Tian i@tianshilei.me 2025-09-24T15:12:02+00:00 2195fe7e018db3d9a6c2e392a2bf8591859b872f On new targets like `gfx1250`, the buffer resource (V#) now uses this format: ``` base (57-bit): resource[56:0] num_records (45-bit): resource[101:57] reserved (6-bit): resource[107:102] stride (14-bit): resource[121:108] ``` This PR changes the type of `num_records` from `i32` to `i64` in both builtin and intrinsic, and also adds the support for lowering the new format. Fixes SWDEV-554034. --------- Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak@amd.com> 
On new targets like `gfx1250`, the buffer resource (V#) now uses this
format:

```
base (57-bit): resource[56:0]
num_records (45-bit): resource[101:57]
reserved (6-bit): resource[107:102]
stride (14-bit): resource[121:108]
```

This PR changes the type of `num_records` from `i32` to `i64` in both
builtin and intrinsic, and also adds the support for lowering the new
format.

Fixes SWDEV-554034.

---------

Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak@amd.com>
 [AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#158754) 2025-09-16T09:26:32+00:00 Stanislav Mekhanoshin Stanislav.Mekhanoshin@amd.com 2025-09-16T09:26:32+00:00 76efbc068a6ab6ffa10b801df07155a6a69530e7 






[AMDGPU] Support lowering of cluster related instrinsics (#157978)
2025-09-13T01:11:17+00:00

Shilei Tian
i@tianshilei.me

2025-09-13T01:11:17+00:00

1180c2ced008e33b0a4b2b91b3cb24724f06147c

Since many code are connected, this also changes how workgroup id is lowered.

Co-authored-by: Jay Foad <jay.foad@amd.com>
Co-authored-by: Ivan Kosarev <ivan.kosarev@amd.com>




Since many code are connected, this also changes how workgroup id is lowered.

Co-authored-by: Jay Foad <jay.foad@amd.com>
Co-authored-by: Ivan Kosarev <ivan.kosarev@amd.com>






[AMDGPU][Legalizer] Avoid pack/unpack for G_FSHR (#156796)
2025-09-04T23:12:57+00:00

Anshil Gandhi
95053726+gandhi56@users.noreply.github.com

2025-09-04T23:12:57+00:00

c6899193ed9b4818dcd20301f36992066c1776d5

Scalarize G_FSHR only if the subtarget does not support V2S16 type.




Scalarize G_FSHR only if the subtarget does not support V2S16 type.






[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
2025-09-04T09:19:25+00:00

Pierre van Houtryve
pierre.vanhoutryve@amd.com

2025-09-04T09:19:25+00:00

e2bd10cf16c3f90813de5b64f348ece035a6bb68

- Add clang built-ins + sema/codegen
- Add IR Intrinsic + verifier
- Add DAG/GlobalISel codegen for the intrinsics
- Add lowering in SIMemoryLegalizer using a MMO flag.




- Add clang built-ins + sema/codegen
- Add IR Intrinsic + verifier
- Add DAG/GlobalISel codegen for the intrinsics
- Add lowering in SIMemoryLegalizer using a MMO flag.






[AMDGPU] Remove `ApproxFuncFPMath` uses (#155578)
2025-08-28T03:09:01+00:00

paperchalice
liujunchang97@outlook.com

2025-08-28T03:09:01+00:00

595573d1edeb0896aeeca84ac5146e11c937305e

One of options in `resetTargetOptions`, this removes `ApproxFuncFPMath`
in AMDGPU part.




One of options in `resetTargetOptions`, this removes `ApproxFuncFPMath`
in AMDGPU part.






[AMDGPU] Narrow only on store to pow of 2 mem location (#150093)
2025-08-18T15:04:27+00:00

Tiger Ding
38360323+zerogtiger@users.noreply.github.com

2025-08-18T15:04:27+00:00

4ab14685a0b96b48f8fd77ead55c1816668cac18

Lowering in GlobalISel for AMDGPU previously always narrows to i32 on
truncating store regardless of mem size or scalar size, causing issues
with types like i65 which is first extended to i128 then stored as i64 +
i8 to i128 locations. Narrowing only on store to pow of 2 mem location
ensures only narrowing to mem size near end of legalization.

This LLVM defect was identified via the AMD Fuzzing project.




Lowering in GlobalISel for AMDGPU previously always narrows to i32 on
truncating store regardless of mem size or scalar size, causing issues
with types like i65 which is first extended to i128 then stored as i64 +
i8 to i128 locations. Narrowing only on store to pow of 2 mem location
ensures only narrowing to mem size near end of legalization.

This LLVM defect was identified via the AMD Fuzzing project.






[AMDGPU] Per-subtarget DPP instruction classification (#153096)
2025-08-11T22:41:02+00:00

Stanislav Mekhanoshin
Stanislav.Mekhanoshin@amd.com

2025-08-11T22:41:02+00:00

ea14834966ad666856246f24de46397cbfc932eb

This is NFCI at this point.




This is NFCI at this point.