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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>AMDGPU: Remove AMDGPUInstrInfo class (#144984)</title>
<updated>2025-06-20T09:26:56+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-20T09:26:56+00:00</published>
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<id>dd4776d429bd20050c80749f669367a0574520c8</id>
<content type='text'>
This was never constructed and only provided one static helper
function.</content>
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<pre>
This was never constructed and only provided one static helper
function.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU/GlobalISel: Use correct type for intrinsic ID</title>
<updated>2024-05-30T12:31:19+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-05-30T12:25:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=08d168c56d303c4e6a2e85e56953c3cb98c6092c'/>
<id>08d168c56d303c4e6a2e85e56953c3cb98c6092c</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"</title>
<updated>2023-07-27T09:19:17+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2023-07-27T09:19:17+00:00</published>
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<id>7c760b224bc4581a7a962ae7ded098a260d19500</id>
<content type='text'>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
</content>
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<pre>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"</title>
<updated>2023-07-27T04:44:24+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2023-07-27T04:44:24+00:00</published>
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<id>d0f7850b01cf17e50a4f4b00e3b84dded94df6b8</id>
<content type='text'>
This reverts commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.

The changes did not cover all occurrences of the deteleted function
MachineInstr::getIntrinsicID().
</content>
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<pre>
This reverts commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.

The changes did not cover all occurrences of the deteleted function
MachineInstr::getIntrinsicID().
</pre>
</div>
</content>
</entry>
<entry>
<title>[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR</title>
<updated>2023-07-27T04:30:45+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2023-07-27T04:30:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=baa3386edb11a2f9bcadda8cf58d56f3707c39fa'/>
<id>baa3386edb11a2f9bcadda8cf58d56f3707c39fa</id>
<content type='text'>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Fix LOD bias in A16 combine</title>
<updated>2022-01-21T11:09:06+00:00</updated>
<author>
<name>Sebastian Neubauer</name>
<email>Sebastian.Neubauer@amd.com</email>
</author>
<published>2021-12-20T14:11:01+00:00</published>
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<id>0530fdbbbb84ea3024a4a8f7156ff716f00ffd48</id>
<content type='text'>
As the codegen fix in D111754, the LOD bias needs to be converted to 16
bits. Fix this in the combine.

Differential Revision: https://reviews.llvm.org/D116038
</content>
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<pre>
As the codegen fix in D111754, the LOD bias needs to be converted to 16
bits. Fix this in the combine.

Differential Revision: https://reviews.llvm.org/D116038
</pre>
</div>
</content>
</entry>
<entry>
<title>[Target] Remove unused forward declarations (NFC)</title>
<updated>2022-01-02T18:20:15+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2022-01-02T18:20:15+00:00</published>
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<id>41bfac6aed1817831e7b83994f4963f604987bd5</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][NFC] Fix typos</title>
<updated>2021-11-12T10:37:21+00:00</updated>
<author>
<name>Neubauer, Sebastian</name>
<email>Sebastian.Neubauer@amd.com</email>
</author>
<published>2021-11-11T14:58:42+00:00</published>
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<id>d1f45ed58f3a7bdca69b93f548682754dd67d80f</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D113672
</content>
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<pre>
Differential Revision: https://reviews.llvm.org/D113672
</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][AMDGPU] Reduce include files dependency.</title>
<updated>2021-01-07T19:22:05+00:00</updated>
<author>
<name>dfukalov</name>
<email>daniil.fukalov@amd.com</email>
</author>
<published>2020-12-25T15:52:14+00:00</published>
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<id>6a87e9b08bf093ba3ccba8650b89f4d337c497f4</id>
<content type='text'>
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813
</content>
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<pre>
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Use tablegen for argument indices</title>
<updated>2020-10-05T09:50:52+00:00</updated>
<author>
<name>Sebastian Neubauer</name>
<email>sebastian.neubauer@amd.com</email>
</author>
<published>2020-09-30T12:15:24+00:00</published>
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<id>6a089ce0e40abbe4e0f26f05540e3caa60d98a29</id>
<content type='text'>
Use tablegen generic tables to get the index of image intrinsic
arguments.
Before, the computation of which image intrinsic argument is at which
index was scattered in a few places, tablegen, the SDag instruction
selection and GlobalISel. This patch changes that, so only tablegen
contains code to compute indices and the ImageDimIntrinsicInfo table
provides these information.

Differential Revision: https://reviews.llvm.org/D86270
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use tablegen generic tables to get the index of image intrinsic
arguments.
Before, the computation of which image intrinsic argument is at which
index was scattered in a few places, tablegen, the SDag instruction
selection and GlobalISel. This patch changes that, so only tablegen
contains code to compute indices and the ImageDimIntrinsicInfo table
provides these information.

Differential Revision: https://reviews.llvm.org/D86270
</pre>
</div>
</content>
</entry>
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