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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU] Fold fmed3 when inputs include infinity (#144824)</title>
<updated>2025-06-24T12:44:17+00:00</updated>
<author>
<name>Darren Wihandi</name>
<email>65404740+fairywreath@users.noreply.github.com</email>
</author>
<published>2025-06-24T12:44:17+00:00</published>
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<id>9f3931b659f628111f0a8484eef952d82e6474c1</id>
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<pre>
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<entry>
<title>[AMDGPU] Support D16 folding for image.sample with multiple extractelement and fptrunc users (#141758)</title>
<updated>2025-06-18T01:00:07+00:00</updated>
<author>
<name>Harrison Hao</name>
<email>57025411+harrisonGPU@users.noreply.github.com</email>
</author>
<published>2025-06-18T01:00:07+00:00</published>
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<id>0defde8e06338cbe968d55d1d9e8581d55f3ae2b</id>
<content type='text'>
Now we only support D16 folding for `image sample` instructions with a
single user: a `fptrunc` to half.
However, we can actually support D16 folding for image.sample
instructions with multiple users,
as long as each user follows the pattern of extractelement followed by
fptrunc to half.
For example:
```
  %sample = call &lt;4 x float&gt; @llvm.amdgcn.image.sample
  %e0 = extractelement &lt;4 x float&gt; %sample, i32 0
  %h0 = fptrunc float %e0 to half
  %e1 = extractelement &lt;4 x float&gt; %sample, i32 1
  %h1 = fptrunc float %e1 to half
  %e2 = extractelement &lt;4 x float&gt; %sample, i32 2
  %h2 = fptrunc float %e2 to half
```
This change enables D16 folding for such cases and avoids generating
`v_cvt_f16_f32_e32` instructions.</content>
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<pre>
Now we only support D16 folding for `image sample` instructions with a
single user: a `fptrunc` to half.
However, we can actually support D16 folding for image.sample
instructions with multiple users,
as long as each user follows the pattern of extractelement followed by
fptrunc to half.
For example:
```
  %sample = call &lt;4 x float&gt; @llvm.amdgcn.image.sample
  %e0 = extractelement &lt;4 x float&gt; %sample, i32 0
  %h0 = fptrunc float %e0 to half
  %e1 = extractelement &lt;4 x float&gt; %sample, i32 1
  %h1 = fptrunc float %e1 to half
  %e2 = extractelement &lt;4 x float&gt; %sample, i32 2
  %h2 = fptrunc float %e2 to half
```
This change enables D16 folding for such cases and avoids generating
`v_cvt_f16_f32_e32` instructions.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Move fpenvIEEEMode into TTI (#141945)</title>
<updated>2025-06-17T23:13:57+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-17T23:13:57+00:00</published>
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<id>af65cb68f553759eac307edda87ff7d8b5fdffa9</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Detect trivially uniform arguments in InstCombine (#129897)</title>
<updated>2025-06-09T11:06:03+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-06-09T11:06:03+00:00</published>
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<id>6b25f4439c2123402afbb2436745904166680dac</id>
<content type='text'>
Update one test to use an SGPR argument as the simplest way of getting a
uniform value.</content>
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Update one test to use an SGPR argument as the simplest way of getting a
uniform value.</pre>
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</content>
</entry>
<entry>
<title>[ValueTracking] Make Depth last default arg (NFC) (#142384)</title>
<updated>2025-06-03T16:12:24+00:00</updated>
<author>
<name>Ramkumar Ramachandra</name>
<email>ramkumar.ramachandra@codasip.com</email>
</author>
<published>2025-06-03T16:12:24+00:00</published>
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<content type='text'>
Having a finite Depth (or recursion limit) for computeKnownBits is very
limiting, but is currently a load-bearing necessity, as all KnownBits
are recomputed on each call and there is no caching. As a prerequisite
for an effort to remove the recursion limit altogether, either using a
clever caching technique, or writing a easily-invalidable KnownBits
analysis, make the Depth argument in APIs in ValueTracking uniformly the
last argument with a default value. This would aid in removing the
argument when the time comes, as many callers that currently pass 0
explicitly are now updated to omit the argument altogether.</content>
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<pre>
Having a finite Depth (or recursion limit) for computeKnownBits is very
limiting, but is currently a load-bearing necessity, as all KnownBits
are recomputed on each call and there is no caching. As a prerequisite
for an effort to remove the recursion limit altogether, either using a
clever caching technique, or writing a easily-invalidable KnownBits
analysis, make the Depth argument in APIs in ValueTracking uniformly the
last argument with a default value. This would aid in removing the
argument when the time comes, as many callers that currently pass 0
explicitly are now updated to omit the argument altogether.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Make llvm.amdgcn.make.buffer.rsrc propagate poison (#141913)</title>
<updated>2025-05-29T13:38:29+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-29T13:38:29+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Hoist readlane/readfirstlane through unary/binary operands (#129037)</title>
<updated>2025-05-13T10:00:49+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-05-13T10:00:49+00:00</published>
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<id>2278f5e65b487f7df0c613990b72fedba3ae34af</id>
<content type='text'>
When a read(first)lane is used on a binary operator and the intrinsic is
the only user of the operator, we can move the read(first)lane into the
operand if the other operand is uniform.

Unfortunately IC doesn't let us access UniformityAnalysis and thus we
can't truly check uniformity, we have to do with a basic uniformity
check which only allows constants or trivially uniform intrinsics calls.

We can also do the same for unary and cast operators.</content>
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<pre>
When a read(first)lane is used on a binary operator and the intrinsic is
the only user of the operator, we can move the read(first)lane into the
operand if the other operand is uniform.

Unfortunately IC doesn't let us access UniformityAnalysis and thus we
can't truly check uniformity, we have to do with a basic uniformity
check which only allows constants or trivially uniform intrinsics calls.

We can also do the same for unary and cast operators.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Use minimumnum/maximumnum for fmed3 with amdgpu-ieee=0</title>
<updated>2025-05-12T18:31:52+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-12T18:31:52+00:00</published>
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<id>038d357dde4907d39f6a3fabbaf48dc39cf9dc60</id>
<content type='text'>
 (#139546)

Try to respect the signaling nan behavior of the instruction,
so also start the special case fold for src2.</content>
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 (#139546)

Try to respect the signaling nan behavior of the instruction,
so also start the special case fold for src2.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Use minnum instead of maxnum for fmed3 src2-nan fold (#139531)</title>
<updated>2025-05-12T18:26:29+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-12T18:26:29+00:00</published>
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<id>08dd0406c6c8b5418cd05528057bc64f6fa1d52f</id>
<content type='text'>
By the pseudocode in the ISA manual, if any input is a nan it acts
like min3, which will fold to min2 of the other operands. The other
cases fold to min, I'm not sure how this one was wrong.</content>
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<pre>
By the pseudocode in the ISA manual, if any input is a nan it acts
like min3, which will fold to min2 of the other operands. The other
cases fold to min, I'm not sure how this one was wrong.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Disable most fmed3 folds for strictfp (#139530)</title>
<updated>2025-05-12T18:21:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-12T18:21:02+00:00</published>
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