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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU][GlobalISel] Combine for breaking s64 and/or into two s32 insts (#151731)</title>
<updated>2025-08-20T15:32:29+00:00</updated>
<author>
<name>Mirko Brkušanin</name>
<email>Mirko.Brkusanin@amd.com</email>
</author>
<published>2025-08-20T15:32:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=80f3b376b3a5494d5ae17b0c152aaa1782384fab'/>
<id>80f3b376b3a5494d5ae17b0c152aaa1782384fab</id>
<content type='text'>
When either one of the operands is all ones in high or low parts,
splitting these opens up other opportunities for combines. One of two
new instructions will either be removed or become a simple copy.</content>
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<pre>
When either one of the operands is all ones in high or low parts,
splitting these opens up other opportunities for combines. One of two
new instructions will either be removed or become a simple copy.</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)</title>
<updated>2025-03-29T10:51:29+00:00</updated>
<author>
<name>Tim Gymnich</name>
<email>tim@gymni.ch</email>
</author>
<published>2025-03-29T10:51:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1d0005a69ac812ea0ff069052daf4c2ea0242a48'/>
<id>1d0005a69ac812ea0ff069052daf4c2ea0242a48</id>
<content type='text'>
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than
just `KnownBits` in the future</content>
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<pre>
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than
just `KnownBits` in the future</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC] Make AMDGPUCombinerHelper methods const (#121903)</title>
<updated>2025-01-10T15:43:14+00:00</updated>
<author>
<name>Paul Bowen-Huggett</name>
<email>paulhuggett@mac.com</email>
</author>
<published>2025-01-10T15:43:14+00:00</published>
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<id>bbb53d1a8cd37cbb31ec5ec7938a0f24f628c821</id>
<content type='text'>
(This replaces #121740. Sorry for wasting your time.)

This is a follow-up to a previous commit (ee7ca0d) which eliminated
several "TODO: make CombinerHelper methods const" remarks. As promised
in that ealier commit, this change completes the set by also making the
methods of AMDGPUCombinerHelper const so that the Helper member of
AMDGPUPreLegalizerCombinerImpl can be const rather than explicitly
mutable.</content>
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<pre>
(This replaces #121740. Sorry for wasting your time.)

This is a follow-up to a previous commit (ee7ca0d) which eliminated
several "TODO: make CombinerHelper methods const" remarks. As promised
in that ealier commit, this change completes the set by also making the
methods of AMDGPUCombinerHelper const so that the Helper member of
AMDGPUPreLegalizerCombinerImpl can be const rather than explicitly
mutable.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)</title>
<updated>2025-01-06T12:12:38+00:00</updated>
<author>
<name>Vikash Gupta</name>
<email>Vikash.Gupta@amd.com</email>
</author>
<published>2025-01-06T12:12:38+00:00</published>
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<id>fd6f8b3ce33cc2cbe378f8f1b391f3f40fa7bd54</id>
<content type='text'>
This combine pattern perform the below transformation.

fmul x, select(y, A, B)      -&gt; fldexp (x, select i32 (y, a, b))
fmul x, select(y, -A, -B)   -&gt; fldexp ((fneg x), select i32 (y, a, b))

where, A=2^a &amp; B=2^b ; a and b are integers.

It is a follow-up PR to implement the above combine for globalIsel, as
the corresponding DAG combine has been done for SelectionDAG Isel
(#111109)</content>
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<pre>
This combine pattern perform the below transformation.

fmul x, select(y, A, B)      -&gt; fldexp (x, select i32 (y, a, b))
fmul x, select(y, -A, -B)   -&gt; fldexp ((fneg x), select i32 (y, a, b))

where, A=2^a &amp; B=2^b ; a and b are integers.

It is a follow-up PR to implement the above combine for globalIsel, as
the corresponding DAG combine has been done for SelectionDAG Isel
(#111109)</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU/GlobalISel: Use correct type for intrinsic ID</title>
<updated>2024-05-30T12:31:19+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-05-30T12:25:22+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Remove unneeded calls to setInstrAndDebugLoc in matchers. NFC.</title>
<updated>2024-05-03T14:01:47+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-05-03T14:01:45+00:00</published>
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<id>99ca40849ddaa466756d5da4e292f514f29fcb34</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Min/max changes for GFX12 (#75214)</title>
<updated>2023-12-13T13:18:10+00:00</updated>
<author>
<name>Piotr Sobczak</name>
<email>piotr.sobczak@amd.com</email>
</author>
<published>2023-12-13T13:18:10+00:00</published>
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<id>6eec80133b2c7b3c22bd665ed8a2fa3928296f36</id>
<content type='text'>
Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</content>
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<pre>
Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</pre>
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</content>
</entry>
<entry>
<title>AMDGPU/GlobalISel: Don't pointlessly check for convergent intrinsics</title>
<updated>2023-09-15T20:32:19+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2023-09-15T06:28:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1f15e39d8194885cb0aea618cce12eb416b2129f'/>
<id>1f15e39d8194885cb0aea618cce12eb416b2129f</id>
<content type='text'>
The set of handled intrinsics for fneg combines aren't convergent. The only
case we might want to handle is mov_dpp.
</content>
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<pre>
The set of handled intrinsics for fneg combines aren't convergent. The only
case we might want to handle is mov_dpp.
</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel] convergent intrinsics</title>
<updated>2023-07-31T06:45:39+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2023-07-31T06:44:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d9847cde4841140a95404ea7b7d3a57f8bfbf976'/>
<id>d9847cde4841140a95404ea7b7d3a57f8bfbf976</id>
<content type='text'>
Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets that currently have some support for GlobalISel, the patch
assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154766
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets that currently have some support for GlobalISel, the patch
assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154766
</pre>
</div>
</content>
</entry>
<entry>
<title>Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"</title>
<updated>2023-07-27T09:19:17+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2023-07-27T09:19:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7c760b224bc4581a7a962ae7ded098a260d19500'/>
<id>7c760b224bc4581a7a962ae7ded098a260d19500</id>
<content type='text'>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
</content>
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<pre>
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
</pre>
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</content>
</entry>
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