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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp, branch users/pcc/spr/elf-add-preferred-function-alignment-flag</title>
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<entry>
<title>[AMDGPU] Remove widen-16-bit-ops from CGP (#145483)</title>
<updated>2025-07-16T08:14:19+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-07-16T08:14:19+00:00</published>
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This was already off by default so there is no codegen change.</content>
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This was already off by default so there is no codegen change.</pre>
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</entry>
<entry>
<title>[ValueTracking] Make Depth last default arg (NFC) (#142384)</title>
<updated>2025-06-03T16:12:24+00:00</updated>
<author>
<name>Ramkumar Ramachandra</name>
<email>ramkumar.ramachandra@codasip.com</email>
</author>
<published>2025-06-03T16:12:24+00:00</published>
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<content type='text'>
Having a finite Depth (or recursion limit) for computeKnownBits is very
limiting, but is currently a load-bearing necessity, as all KnownBits
are recomputed on each call and there is no caching. As a prerequisite
for an effort to remove the recursion limit altogether, either using a
clever caching technique, or writing a easily-invalidable KnownBits
analysis, make the Depth argument in APIs in ValueTracking uniformly the
last argument with a default value. This would aid in removing the
argument when the time comes, as many callers that currently pass 0
explicitly are now updated to omit the argument altogether.</content>
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<pre>
Having a finite Depth (or recursion limit) for computeKnownBits is very
limiting, but is currently a load-bearing necessity, as all KnownBits
are recomputed on each call and there is no caching. As a prerequisite
for an effort to remove the recursion limit altogether, either using a
clever caching technique, or writing a easily-invalidable KnownBits
analysis, make the Depth argument in APIs in ValueTracking uniformly the
last argument with a default value. This would aid in removing the
argument when the time comes, as many callers that currently pass 0
explicitly are now updated to omit the argument altogether.</pre>
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</content>
</entry>
<entry>
<title>AMDGPUCodeGenPrepare.cpp - fix MSVC operator precedence warning. NFC.</title>
<updated>2025-06-02T08:47:52+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-06-02T08:45:43+00:00</published>
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</pre>
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<entry>
<title>AMDGPU: Handle other fmin flavors in fract combine (#141987)</title>
<updated>2025-05-29T20:11:01+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-29T20:11:01+00:00</published>
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<id>cc8d253f390e4afc7b275a234f5fcdc976a0af71</id>
<content type='text'>
Since the input is either known not-nan, or we have explicit use
code checking if the input is a nan, any of the 3 is valid to match.</content>
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<pre>
Since the input is either known not-nan, or we have explicit use
code checking if the input is a nan, any of the 3 is valid to match.</pre>
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</entry>
<entry>
<title>[AMDGPU] Handle CreateBinOp not returning BinaryOperator (#137791)</title>
<updated>2025-05-29T17:10:35+00:00</updated>
<author>
<name>anjenner</name>
<email>161845516+anjenner@users.noreply.github.com</email>
</author>
<published>2025-05-29T17:10:35+00:00</published>
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<content type='text'>
AMDGPUCodeGenPrepareImpl::visitBinaryOperator() calls
Builder.CreateBinOp() and casts the resulting Value as a BinaryOperator
without checking, leading to an assert failure in a case found by
fuzzing. In this case, the operands are constant and CreateBinOp does
constant folding so returns a Constant instead of a BinaryOperator.</content>
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<pre>
AMDGPUCodeGenPrepareImpl::visitBinaryOperator() calls
Builder.CreateBinOp() and casts the resulting Value as a BinaryOperator
without checking, leading to an assert failure in a case found by
fuzzing. In this case, the operands are constant and CreateBinOp does
constant folding so returns a Constant instead of a BinaryOperator.</pre>
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</entry>
<entry>
<title>[AMDGPU] Remove unused includes (NFC) (#141376)</title>
<updated>2025-05-24T21:48:46+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-05-24T21:48:46+00:00</published>
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<id>1e8e66217498566a139ab3c38c5333a08550e4fb</id>
<content type='text'>
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.</content>
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<pre>
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.</pre>
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</entry>
<entry>
<title>[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)</title>
<updated>2025-05-16T08:31:03+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-05-16T08:31:03+00:00</published>
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<content type='text'>
For the majority of cases, this is a neutral or positive change.
There are even testcases that greatly benefit from it, but some regressions are possible.
There is #140040 for GlobalISel that'd need to be fixed but it's only a one instruction regression and I think it can be fixed later.

Solves #64591</content>
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<pre>
For the majority of cases, this is a neutral or positive change.
There are even testcases that greatly benefit from it, but some regressions are possible.
There is #140040 for GlobalISel that'd need to be fixed but it's only a one instruction regression and I think it can be fixed later.

Solves #64591</pre>
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</entry>
<entry>
<title>[IRBuilder] Add versions of createInsertVector/createExtractVector that take a uint64_t index. (#138324)</title>
<updated>2025-05-02T23:10:18+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-05-02T23:10:18+00:00</published>
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<id>123758b1f4a8106926d95268ea8dc27158b6393a</id>
<content type='text'>
Most callers want a constant index. Instead of making every caller
create a ConstantInt, we can do it in IRBuilder. This is similar to
createInsertElement/createExtractElement.</content>
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<pre>
Most callers want a constant index. Instead of making every caller
create a ConstantInt, we can do it in IRBuilder. This is similar to
createInsertElement/createExtractElement.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Check for nonnull loads feeding addrspacecast (#138184)</title>
<updated>2025-05-02T11:54:22+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-05-02T11:54:22+00:00</published>
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<id>9060ca01913776cbed78b03e72d7700adc2201b7</id>
<content type='text'>
Handle nonnull loads just like nonnull arguments when checking for
addrspacecasts that are known never null.</content>
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<pre>
Handle nonnull loads just like nonnull arguments when checking for
addrspacecasts that are known never null.</pre>
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</entry>
<entry>
<title>[AMDGPU] Use variadic isa&lt;&gt;. NFC. (#137016)</title>
<updated>2025-04-24T07:19:09+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-04-24T07:19:09+00:00</published>
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</pre>
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