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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)</title>
<updated>2025-01-10T19:39:02+00:00</updated>
<author>
<name>Austin Kerbow</name>
<email>Austin.Kerbow@amd.com</email>
</author>
<published>2025-01-10T19:39:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2e5c2982819625d84e0b61aea0ec00de859f0e95'/>
<id>2e5c2982819625d84e0b61aea0ec00de859f0e95</id>
<content type='text'>
Add a prologue to the kernel entry to handle cases where code designed
for kernarg preloading is executed on hardware equipped with
incompatible firmware. If hardware has compatible firmware the 256 bytes
at the start of the kernel entry will be skipped. This skipping is done
automatically by hardware that supports the feature.

A pass is added which is intended to be run at the very end of the
pipeline to avoid any optimizations that would assume the prologue is a
real predecessor block to the actual code start. In reality we have two
possible entry points for the function. 1. The optimized path that
supports kernarg preloading which begins at an offset of 256 bytes. 2.
The backwards compatible entry point which starts at offset 0.</content>
<content type='xhtml'>
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<pre>
Add a prologue to the kernel entry to handle cases where code designed
for kernarg preloading is executed on hardware equipped with
incompatible firmware. If hardware has compatible firmware the 256 bytes
at the start of the kernel entry will be skipped. This skipping is done
automatically by hardware that supports the feature.

A pass is added which is intended to be run at the very end of the
pipeline to avoid any optimizations that would assume the prologue is a
real predecessor block to the actual code start. In reality we have two
possible entry points for the function. 1. The optimized path that
supports kernarg preloading which begins at an offset of 256 bytes. 2.
The backwards compatible entry point which starts at offset 0.</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][AMDGPU] Assert no bad shift operations will happen (#108416)</title>
<updated>2024-09-24T10:47:57+00:00</updated>
<author>
<name>Georgi Mirazchiyski</name>
<email>georgi.mirazchiyski@codeplay.com</email>
</author>
<published>2024-09-24T10:47:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6cfe6a6b3e9578be80120add7fbe19506f747196'/>
<id>6cfe6a6b3e9578be80120add7fbe19506f747196</id>
<content type='text'>
The assumption in the asserts is based on the fact that no SGPR/VGPR
register Arg mask in the ISelLowering and Legalizer can equal zero. They
are implicitly set to ~0 by default (meaning non-masked) or explicitly
to a non-zero value.
The `optimizeCompareInstr` case is different from the above described.
It requires the mask to be a power-of-two because it's a special-case
optimization, hence in this case we still cannot have an invalid shift.
This commit also silences static analysis tools wrt potential bad shifts
that could result from the output of `countr_zero(Mask)`.</content>
<content type='xhtml'>
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<pre>
The assumption in the asserts is based on the fact that no SGPR/VGPR
register Arg mask in the ISelLowering and Legalizer can equal zero. They
are implicitly set to ~0 by default (meaning non-masked) or explicitly
to a non-zero value.
The `optimizeCompareInstr` case is different from the above described.
It requires the mask to be a power-of-two because it's a special-case
optimization, hence in this case we still cannot have an invalid shift.
This commit also silences static analysis tools wrt potential bad shifts
that could result from the output of `countr_zero(Mask)`.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Add plumbing for private segment size argument (#96445)</title>
<updated>2024-06-25T14:20:51+00:00</updated>
<author>
<name>Nicolai Hähnle</name>
<email>nicolai.haehnle@amd.com</email>
</author>
<published>2024-06-25T14:20:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7e9b49f6b86c8616e6211ec02dbccc3ebb615e79'/>
<id>7e9b49f6b86c8616e6211ec02dbccc3ebb615e79</id>
<content type='text'>
The actual size of scratch/private is determined at dispatch time, so
add more plumbing to request it. Will be used in subsequent change.</content>
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<pre>
The actual size of scratch/private is determined at dispatch time, so
add more plumbing to request it. Will be used in subsequent change.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Miscellaneous clang-format changes (#75186)</title>
<updated>2023-12-12T14:26:04+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-12-12T14:26:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1c6b336395a886c0125462ef338e84ea3a6925e6'/>
<id>1c6b336395a886c0125462ef338e84ea3a6925e6</id>
<content type='text'>
Reformat one table and protect a couple of tables that we don't want to
reformat.</content>
<content type='xhtml'>
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<pre>
Reformat one table and protect a couple of tables that we don't want to
reformat.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add DAG ISel support for preloaded kernel arguments</title>
<updated>2023-09-25T16:32:59+00:00</updated>
<author>
<name>Austin Kerbow</name>
<email>Austin.Kerbow@amd.com</email>
</author>
<published>2023-08-02T00:51:59+00:00</published>
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<id>0455596e1e7fecb6c76de9eba4e2ffc8772eadc2</id>
<content type='text'>
This patch adds the DAG isel changes for kernel argument preloading.
These changes are not usable with older firmware but subsequent patches
in the series will make the codegen backwards compatible. This patch
should only be submitted alongside that subsequent patch.

Preloading here begins from the start of the kernel arguments until the
amount of arguments indicated by the CL flag
amdgpu-kernarg-preload-count.

Aggregates and arguments passed by-ref are not supported.

Special care for the alignment of the kernarg segment is needed as well
as consideration of the alignment of addressable SGPR tuples when we
cannot directly use misaligned large tuples that the arguments are
loaded to.

Reviewed By: bcahoon

Differential Revision: https://reviews.llvm.org/D158579
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds the DAG isel changes for kernel argument preloading.
These changes are not usable with older firmware but subsequent patches
in the series will make the codegen backwards compatible. This patch
should only be submitted alongside that subsequent patch.

Preloading here begins from the start of the kernel arguments until the
amount of arguments indicated by the CL flag
amdgpu-kernarg-preload-count.

Aggregates and arguments passed by-ref are not supported.

Special care for the alignment of the kernarg segment is needed as well
as consideration of the alignment of addressable SGPR tuples when we
cannot directly use misaligned large tuples that the arguments are
loaded to.

Reviewed By: bcahoon

Differential Revision: https://reviews.llvm.org/D158579
</pre>
</div>
</content>
</entry>
<entry>
<title>[amdgpu] Implement lds kernel id intrinsic</title>
<updated>2022-07-19T16:46:19+00:00</updated>
<author>
<name>Jon Chesterfield</name>
<email>jonathanchesterfield@gmail.com</email>
</author>
<published>2022-07-19T16:46:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=3a20597776a5d2920e511d81653b4d2b6ca0c855'/>
<id>3a20597776a5d2920e511d81653b4d2b6ca0c855</id>
<content type='text'>
Implement an intrinsic for use lowering LDS variables to different
addresses from different kernels. This will allow kernels that cannot
reach an LDS variable to avoid wasting space for it.

There are a number of implicit arguments accessed by intrinsic already
so this implementation closely follows the existing handling. It is slightly
novel in that this SGPR is written by the kernel prologue.

It is necessary in the general case to put variables at different addresses
such that they can be compactly allocated and thus necessary for an
indirect function call to have some means of determining where a
given variable was allocated. Claiming an arbitrary SGPR into which
an integer can be written by the kernel, in this implementation based
on metadata associated with that kernel, which is then passed on to
indirect call sites is sufficient to determine the variable address.

The intent is to emit a __const array of LDS addresses and index into it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D125060
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Implement an intrinsic for use lowering LDS variables to different
addresses from different kernels. This will allow kernels that cannot
reach an LDS variable to avoid wasting space for it.

There are a number of implicit arguments accessed by intrinsic already
so this implementation closely follows the existing handling. It is slightly
novel in that this SGPR is written by the kernel prologue.

It is necessary in the general case to put variables at different addresses
such that they can be compactly allocated and thus necessary for an
indirect function call to have some means of determining where a
given variable was allocated. Claiming an arbitrary SGPR into which
an integer can be written by the kernel, in this implementation based
on metadata associated with that kernel, which is then passed on to
indirect call sites is sufficient to determine the variable address.

The intent is to emit a __const array of LDS addresses and index into it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D125060
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] gfx90a support</title>
<updated>2021-02-18T00:01:32+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2021-02-17T21:37:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a8d9d50762c42d726274d3f1126ec97ff96e2a22'/>
<id>a8d9d50762c42d726274d3f1126ec97ff96e2a22</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D96906
</content>
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<pre>
Differential Revision: https://reviews.llvm.org/D96906
</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][AMDGPU] Reduce include files dependency.</title>
<updated>2021-01-07T19:22:05+00:00</updated>
<author>
<name>dfukalov</name>
<email>daniil.fukalov@amd.com</email>
</author>
<published>2020-12-25T15:52:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6a87e9b08bf093ba3ccba8650b89f4d337c497f4'/>
<id>6a87e9b08bf093ba3ccba8650b89f4d337c497f4</id>
<content type='text'>
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813
</content>
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<pre>
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813
</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Use MCRegister for preloaded arguments</title>
<updated>2020-07-20T17:34:28+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-07-20T17:25:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ce76d15a70d036f4a307a41b91b5051ff492b2e9'/>
<id>ce76d15a70d036f4a307a41b91b5051ff492b2e9</id>
<content type='text'>
Attempt to fix build error with ancient GCC
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<pre>
Attempt to fix build error with ancient GCC
</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU/GlobalISel: Add types to special inputs</title>
<updated>2020-07-06T21:00:55+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-07-05T17:17:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f25d020c2ec7cb1971fa56b99381d416799d8145'/>
<id>f25d020c2ec7cb1971fa56b99381d416799d8145</id>
<content type='text'>
When passing special ABI inputs, we have no existing context for the
type to use.
</content>
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<pre>
When passing special ABI inputs, we have no existing context for the
type to use.
</pre>
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</content>
</entry>
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