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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPU.td, branch users/nico/python-2</title>
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<title>AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)</title>
<updated>2025-07-01T18:08:49+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-07-01T18:08:49+00:00</published>
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These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</content>
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These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</pre>
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<entry>
<title>AMDGPU: Add MC layer support for load transpose instructions for gfx1250 (#146024)</title>
<updated>2025-06-27T05:30:31+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-06-27T05:30:31+00:00</published>
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Co-authored with @jayfoad</content>
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Co-authored with @jayfoad</pre>
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<entry>
<title>AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)</title>
<updated>2025-06-25T05:44:35+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-06-25T05:44:35+00:00</published>
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<entry>
<title>AMDGPU: Remove export and related instructions from gfx1250 support (#145624)</title>
<updated>2025-06-25T02:59:26+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-06-25T02:59:26+00:00</published>
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<entry>
<title>AMDGPU: Remove Formatted MUBUF instructions from gfx1250 support (#145590)</title>
<updated>2025-06-24T21:17:13+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-06-24T21:17:13+00:00</published>
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<entry>
<title>AMDGPU: Remove MTBUF instructions from gfx1250 support (#145563)</title>
<updated>2025-06-24T18:59:13+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-06-24T18:59:13+00:00</published>
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<entry>
<title>[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)</title>
<updated>2025-06-24T09:09:36+00:00</updated>
<author>
<name>Diana Picus</name>
<email>Diana-Magda.Picus@amd.com</email>
</author>
<published>2025-06-24T09:09:36+00:00</published>
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Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.</content>
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Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.</pre>
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<entry>
<title>[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (#145152)</title>
<updated>2025-06-22T19:52:05+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>rampitec@users.noreply.github.com</email>
</author>
<published>2025-06-22T19:52:05+00:00</published>
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<entry>
<title>[AMDGPU] Rename call instructions from b64 to i64 (#145103)</title>
<updated>2025-06-22T04:42:09+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>rampitec@users.noreply.github.com</email>
</author>
<published>2025-06-22T04:42:09+00:00</published>
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<content type='text'>
These get renamed in gfx1250 and on from B64 to I64:

  S_CALL_I64
  S_GET_PC_I64
  S_RFE_I64
  S_SET_PC_I64
  S_SWAP_PC_I64</content>
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These get renamed in gfx1250 and on from B64 to I64:

  S_CALL_I64
  S_GET_PC_I64
  S_RFE_I64
  S_SET_PC_I64
  S_SWAP_PC_I64</pre>
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<entry>
<title>[AMDGPU] Add s_wait_xcnt gfx1250 instruction (#145086)</title>
<updated>2025-06-20T19:28:18+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>rampitec@users.noreply.github.com</email>
</author>
<published>2025-06-20T19:28:18+00:00</published>
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