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<title>llvm-project.git/llvm/lib/Target/AMDGPU/AMDGPU.td, branch users/mingmingl-llvm/samplefdo-profile-format</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Revert "[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)" (#157639)</title>
<updated>2025-09-10T08:20:59+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-09-10T08:20:59+00:00</published>
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<id>dcaa29c8ed6cc3b62368cdd609f2d05a25541366</id>
<content type='text'>
This reverts commit be17791f2624f22b3ed24a2539406164a379125d.

This is not necessary for gfx1250 anymore.</content>
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<pre>
This reverts commit be17791f2624f22b3ed24a2539406164a379125d.

This is not necessary for gfx1250 anymore.</pre>
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<entry>
<title>AMDGPU: Fix mis-selecting saddr flat atomics on gfx9 (#156860)</title>
<updated>2025-09-04T23:38:23+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-04T23:38:23+00:00</published>
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<id>4aaf47ee4c8fda3b59013f0a3c01dcc1f73b429f</id>
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This would select the pseudo and then crash when the MC instruction
was used. I believe this has been broken since 9912ccb0b4d17</content>
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<pre>
This would select the pseudo and then crash when the MC instruction
was used. I believe this has been broken since 9912ccb0b4d17</pre>
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</entry>
<entry>
<title>[AMDGPU] Add s_set_vgpr_msb gfx1250 instruction (#156524)</title>
<updated>2025-09-02T21:22:57+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-09-02T21:22:57+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)</title>
<updated>2025-09-02T07:37:43+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-09-02T07:37:43+00:00</published>
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<content type='text'>
Re-enable it by adding a wait on vm_vsrc before every barrier "start"
instruction in GFX10/11/12 CU mode.

This is a less strong wait than what we do without BackOffBarrier, thus
this shouldn't introduce
any new guarantees that can be abused, instead it relaxes the guarantees
we have now to the bare
minimum needed to support the behavior users want (fence release +
barrier works).

There is an exact memory model in the works which will be documented
separately.</content>
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<pre>
Re-enable it by adding a wait on vm_vsrc before every barrier "start"
instruction in GFX10/11/12 CU mode.

This is a less strong wait than what we do without BackOffBarrier, thus
this shouldn't introduce
any new guarantees that can be abused, instead it relaxes the guarantees
we have now to the bare
minimum needed to support the behavior users want (fence release +
barrier works).

There is an exact memory model in the works which will be documented
separately.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Add target feature for aligned VGPR requirement (#155336)</title>
<updated>2025-08-26T01:36:51+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-08-26T01:36:51+00:00</published>
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<id>3134e696e4d151f72b734e9d7a9aad80556d0b2d</id>
<content type='text'>
This now applies to gfx90a+ and gfx1250, so add a dedicated feature
for it so the feature check can be composed correctly with unrelated
properties. Probably would be better to invert this, but that turns
out to be difficult given the current assumptions.</content>
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<pre>
This now applies to gfx90a+ and gfx1250, so add a dedicated feature
for it so the feature check can be composed correctly with unrelated
properties. Probably would be better to invert this, but that turns
out to be difficult given the current assumptions.</pre>
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</entry>
<entry>
<title>[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)</title>
<updated>2025-08-14T19:52:00+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-14T19:52:00+00:00</published>
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</pre>
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<entry>
<title>[AMDGPU] s_get_shader_cycles_u64 gfx1250 instruction (#152390)</title>
<updated>2025-08-06T22:32:28+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-06T22:32:28+00:00</published>
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It is the same as reading SHADER_CYCLES_LO and SHADER_CYCLES_HI
but with a single instruction.</content>
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<pre>
It is the same as reading SHADER_CYCLES_LO and SHADER_CYCLES_HI
but with a single instruction.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] System scope atomics are emulated over PCIe in gfx1250 (#152369)</title>
<updated>2025-08-06T20:08:12+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-06T20:08:12+00:00</published>
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<id>c2eddec4ff42eca8a93e3f8a0531dfb6e60a61ca</id>
<content type='text'>
HW will emulate unsupported PCIe atomics via CAS loop, we do not need to
expand these anymore.</content>
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<pre>
HW will emulate unsupported PCIe atomics via CAS loop, we do not need to
expand these anymore.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)</title>
<updated>2025-08-05T21:35:48+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-05T21:35:48+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] gfx1250 v_perm_pk16_* instructions (#151773)</title>
<updated>2025-08-02T03:12:35+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-08-02T03:12:35+00:00</published>
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