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<title>llvm-project.git/llvm/lib/Object/ELFObjectFile.cpp, branch users/meinersbur/flang_runtime_split-headers</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[Hexagon] Add V75 support to compiler and assembler (#120773)</title>
<updated>2024-12-20T20:01:58+00:00</updated>
<author>
<name>Ikhlas Ajbar</name>
<email>iajbar@quicinc.com</email>
</author>
<published>2024-12-20T20:01:58+00:00</published>
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<id>8b37c1c71bf66274251db35b742f8f4013be2f52</id>
<content type='text'>
This patch introduces support for the Hexagon V75 architecture. It
includes instruction formats, definitions, encodings, scheduling
classes, and builtins/intrinsics.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch introduces support for the Hexagon V75 architecture. It
includes instruction formats, definitions, encodings, scheduling
classes, and builtins/intrinsics.</pre>
</div>
</content>
</entry>
<entry>
<title>[Object] Remove unused includes (NFC) (#116750)</title>
<updated>2024-11-20T03:42:09+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-20T03:42:09+00:00</published>
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<id>e9c8106a90d49e75bac87341ade57c6049357a97</id>
<content type='text'>
Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Add gfx950 subtarget definitions (#116307)</title>
<updated>2024-11-18T18:41:14+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-11-18T18:41:14+00:00</published>
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<id>a6fc489bb7a2e9fb3a7f70cccc181e4ee70374bf</id>
<content type='text'>
Mostly a stub, but adds some baseline tests and
tests for removed instructions.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Mostly a stub, but adds some baseline tests and
tests for removed instructions.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Introduce a new generic target `gfx9-4-generic` (#115190)</title>
<updated>2024-11-13T04:11:05+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-11-13T04:11:05+00:00</published>
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<id>de0fd64bedd23660f557833cc0108c3fb2be3918</id>
<content type='text'>
This patch introduces a new generic target, `gfx9-4-generic`. Since it doesn’t support FP8 and XF32-related instructions, the patch includes several code reorganizations to accommodate these changes.</content>
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<pre>
This patch introduces a new generic target, `gfx9-4-generic`. Since it doesn’t support FP8 and XF32-related instructions, the patch includes several code reorganizations to accommodate these changes.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add a new target for gfx1153 (#113138)</title>
<updated>2024-10-23T03:56:58+00:00</updated>
<author>
<name>Carl Ritson</name>
<email>carl.ritson@amd.com</email>
</author>
<published>2024-10-23T03:56:58+00:00</published>
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<id>076aac59acbe7555b922e77886e4428f1aa1cd0b</id>
<content type='text'>
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[BPF] Make llvm-objdump disasm default cpu v4 (#102166)</title>
<updated>2024-08-07T01:23:46+00:00</updated>
<author>
<name>yonghong-song</name>
<email>yhs@fb.com</email>
</author>
<published>2024-08-07T01:23:46+00:00</published>
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<id>03958680b23dafd961ea0606c77d8e6bc8d80781</id>
<content type='text'>
Currently, with the following example,
  $ cat t.c
  void foo(int a, _Atomic int *b)
  {
   *b &amp;= a;
  }
  $ clang --target=bpf -O2 -c -mcpu=v3 t.c
  $ llvm-objdump -d t.o
  t.o:    file format elf64-bpf

  Disassembly of section .text:

  0000000000000000 &lt;foo&gt;:
       0:       c3 12 00 00 51 00 00 00 &lt;unknown&gt;
       1:       95 00 00 00 00 00 00 00 exit

Basically, the default cpu for llvm-objdump is v1 and it won't be able
to decode insn properly.

If we add --mcpu=v3 to llvm-objdump command line, we will have
  $ llvm-objdump -d --mcpu=v3 t.o

  t.o:    file format elf64-bpf

  Disassembly of section .text:

  0000000000000000 &lt;foo&gt;:
0: c3 12 00 00 51 00 00 00 w1 = atomic_fetch_and((u32 *)(r2 + 0x0), w1)
       1:       95 00 00 00 00 00 00 00 exit

The atomic_fetch_and insn can be decoded properly. Using latest cpu
version --mcpu=v4 can also decode properly like the above --mcpu=v3.

To avoid the above '&lt;unknown&gt;' decoding with common 'llvm-objdump -d
t.o', this patch marked the default cpu for llvm-objdump with the
current highest cpu number v4 in ELFObjectFileBase::tryGetCPUName(). The
cpu number in ELFObjectFileBase::tryGetCPUName() will be adjusted in the
future if cpu number is increased e.g. v5 etc. Such an approach also
aligns with gcc-bpf as discussed in [1].

Six bpf unit tests are affected with this change. I changed test output
for three unit tests and added --mcpu=v1 for the other three unit tests,
to demonstrate the default (cpu v4) behavior and explicit --mcpu=v1
behavior.

[1]
https://lore.kernel.org/bpf/6f32c0a1-9de2-4145-92ea-be025362182f@linux.dev/T/#m0f7e63c390bc8f5a5523e7f2f0537becd4205200

Co-authored-by: Yonghong Song &lt;yonghong.song@linux.dev&gt;</content>
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<pre>
Currently, with the following example,
  $ cat t.c
  void foo(int a, _Atomic int *b)
  {
   *b &amp;= a;
  }
  $ clang --target=bpf -O2 -c -mcpu=v3 t.c
  $ llvm-objdump -d t.o
  t.o:    file format elf64-bpf

  Disassembly of section .text:

  0000000000000000 &lt;foo&gt;:
       0:       c3 12 00 00 51 00 00 00 &lt;unknown&gt;
       1:       95 00 00 00 00 00 00 00 exit

Basically, the default cpu for llvm-objdump is v1 and it won't be able
to decode insn properly.

If we add --mcpu=v3 to llvm-objdump command line, we will have
  $ llvm-objdump -d --mcpu=v3 t.o

  t.o:    file format elf64-bpf

  Disassembly of section .text:

  0000000000000000 &lt;foo&gt;:
0: c3 12 00 00 51 00 00 00 w1 = atomic_fetch_and((u32 *)(r2 + 0x0), w1)
       1:       95 00 00 00 00 00 00 00 exit

The atomic_fetch_and insn can be decoded properly. Using latest cpu
version --mcpu=v4 can also decode properly like the above --mcpu=v3.

To avoid the above '&lt;unknown&gt;' decoding with common 'llvm-objdump -d
t.o', this patch marked the default cpu for llvm-objdump with the
current highest cpu number v4 in ELFObjectFileBase::tryGetCPUName(). The
cpu number in ELFObjectFileBase::tryGetCPUName() will be adjusted in the
future if cpu number is increased e.g. v5 etc. Such an approach also
aligns with gcc-bpf as discussed in [1].

Six bpf unit tests are affected with this change. I changed test output
for three unit tests and added --mcpu=v1 for the other three unit tests,
to demonstrate the default (cpu v4) behavior and explicit --mcpu=v1
behavior.

[1]
https://lore.kernel.org/bpf/6f32c0a1-9de2-4145-92ea-be025362182f@linux.dev/T/#m0f7e63c390bc8f5a5523e7f2f0537becd4205200

Co-authored-by: Yonghong Song &lt;yonghong.song@linux.dev&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm-objdump] -r: support CREL</title>
<updated>2024-07-08T16:14:34+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2024-07-08T16:14:34+00:00</published>
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<id>2f37a22f10a1128c695bc469871a9101edce853e</id>
<content type='text'>
Extract the llvm-readelf decoder to `decodeCrel` (#91280) and reuse it
for llvm-objdump.

Because the section representation of LLVMObject (`SectionRef`) is
64-bit, insufficient to hold all decoder states, `section_rel_begin` is
modified to decode CREL eagerly and hold the decoded relocations inside
ELFObjectFile&lt;ELFT&gt;.

The test is adapted from llvm/test/tools/llvm-readobj/ELF/crel.test.

Pull Request: https://github.com/llvm/llvm-project/pull/97382
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Extract the llvm-readelf decoder to `decodeCrel` (#91280) and reuse it
for llvm-objdump.

Because the section representation of LLVMObject (`SectionRef`) is
64-bit, insufficient to hold all decoder states, `section_rel_begin` is
modified to decode CREL eagerly and hold the decoded relocations inside
ELFObjectFile&lt;ELFT&gt;.

The test is adapted from llvm/test/tools/llvm-readobj/ELF/crel.test.

Pull Request: https://github.com/llvm/llvm-project/pull/97382
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add a new target gfx1152 (#94534)</title>
<updated>2024-06-06T16:16:11+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-06-06T16:16:11+00:00</published>
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<id>1ca0055f45abe7e4d484a0af457fc20be318c8e2</id>
<content type='text'>
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Add gfx12-generic target (#93875)</title>
<updated>2024-05-31T16:46:44+00:00</updated>
<author>
<name>Konstantin Zhuravlyov</name>
<email>kzhuravl_dev@outlook.com</email>
</author>
<published>2024-05-31T16:46:44+00:00</published>
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<id>775f1cd34daffa3e188bddcd600b6ccad1f72d24</id>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)</title>
<updated>2024-04-23T22:12:36+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-04-23T22:12:36+00:00</published>
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<id>733a87783cfac7e6bac2c14bc3749ddca879e2be</id>
<content type='text'>
This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.

This will allow us to generate part of RISCVISAInfo.cpp using tablegen.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.

This will allow us to generate part of RISCVISAInfo.cpp using tablegen.</pre>
</div>
</content>
</entry>
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