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<title>llvm-project.git/llvm/lib/CodeGen/VirtRegMap.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (#140002)</title>
<updated>2025-05-22T15:07:52+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-22T15:07:52+00:00</published>
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<id>1fdf02ad5a4ca155017eea22688365a20aab077c</id>
<content type='text'>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove unused variable 'ID' (NFC)</title>
<updated>2025-04-30T11:15:27+00:00</updated>
<author>
<name>Jie Fu</name>
<email>jiefu@tencent.com</email>
</author>
<published>2025-04-30T11:15:27+00:00</published>
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<id>6e43cdbc25e90d88251d69519822713afc20108c</id>
<content type='text'>
/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp:225:15:
error: unused variable 'ID' [-Werror,-Wunused-variable]
  static char ID;
              ^
1 error generated.
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp:225:15:
error: unused variable 'ID' [-Werror,-Wunused-variable]
  static char ID;
              ^
1 error generated.
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)</title>
<updated>2025-04-30T08:40:46+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2025-04-30T08:40:46+00:00</published>
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<id>e91cbd4f299fd3f42928aff63f5d95f07be3f7fc</id>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>RegAlloc: Use new approach to handling failed allocations (#128469)</title>
<updated>2025-02-26T08:34:47+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-02-26T08:34:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1a114fa302b48fc761a58a8d3be5962d92fa581b'/>
<id>1a114fa302b48fc761a58a8d3be5962d92fa581b</id>
<content type='text'>
This fixes an assert after allocation failure.

Rather than collecting failed virtual registers and hacking
on the uses after the fact, directly hack on the uses and rewrite
the registers to the dummy assignment immediately.

Previously we were bypassing LiveRegMatrix and directly assigning
in the VirtRegMap. This resulted in inconsistencies where illegal
overlapping assignments were missing. Rather than try to hack in
some system to manage these in LiveRegMatrix (i.e. hacking around
cases with invalid iterators), avoid this by directly using the
physreg. This should also allow removal of special casing in
virtregrewriter for failed allocations.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This fixes an assert after allocation failure.

Rather than collecting failed virtual registers and hacking
on the uses after the fact, directly hack on the uses and rewrite
the registers to the dummy assignment immediately.

Previously we were bypassing LiveRegMatrix and directly assigning
in the VirtRegMap. This resulted in inconsistencies where illegal
overlapping assignments were missing. Rather than try to hack in
some system to manage these in LiveRegMatrix (i.e. hacking around
cases with invalid iterators), avoid this by directly using the
physreg. This should also allow removal of special casing in
virtregrewriter for failed allocations.</pre>
</div>
</content>
</entry>
<entry>
<title>VirtRegRewriter: Fix verifier errors after regalloc failures (#128280)</title>
<updated>2025-02-26T06:19:49+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-02-26T06:19:49+00:00</published>
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<id>b5dd1fedc5dc3c2e76069ac7536b889915acc2ae</id>
<content type='text'>
</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Use MCRegister instead of MCPhysReg in VirtRegMap. NFC</title>
<updated>2025-01-19T07:03:03+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-19T06:54:58+00:00</published>
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<id>0a44d3a57f03e8263f1509eb397201c9e07b21aa</id>
<content type='text'>
The callers of these methods already use MCRegister.
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The callers of these methods already use MCRegister.
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)</title>
<updated>2025-01-14T12:59:31+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-01-14T12:59:31+00:00</published>
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<id>0d71b3e4031e7b18a5947bdea076839e5a56d202</id>
<content type='text'>
</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)</title>
<updated>2024-12-16T01:52:49+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-12-16T01:52:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=61f99a1c75e9dc84b70d6f2a660e99c1ac182e5b'/>
<id>61f99a1c75e9dc84b70d6f2a660e99c1ac182e5b</id>
<content type='text'>
Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register. Also reduces the number
of redundant errors emitted, particularly with fast.

This is still broken in the case of undef uses. There are additional
complications in greedy and fast, so leave it for a separate fix.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register. Also reduces the number
of redundant errors emitted, particularly with fast.

This is still broken in the case of undef uses. There are additional
complications in greedy and fast, so leave it for a separate fix.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen][PM] Initialize analyses with isAnalysis=true (#118779)</title>
<updated>2024-12-06T09:55:54+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2024-12-06T09:55:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=49abcd207fe26ea0fc7170e66f1b0b22f1d853d3'/>
<id>49abcd207fe26ea0fc7170e66f1b0b22f1d853d3</id>
<content type='text'>
Analyses should be marked as analyses.

Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Analyses should be marked as analyses.

Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)</title>
<updated>2024-12-06T09:46:07+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2024-12-06T09:46:07+00:00</published>
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<id>2c7ece2e8cf58d607f870ca9f02302df8aaa75d4</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
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