Currently, the spill weight is only determined by isDef/isUse and block frequency. However, for registers with different register classes, the costs of spilling them are different. For example, for `LMUL>1` registers (in which, several physical registers compound a bigger logical register), the costs are larger than `LMUL=1` case (in which, there is only one physical register). To solve this problem, a new target hook `getSpillWeightScaleFactor` is added. Targets can override the default factor (which is `1.0`) according to the register class. For RISC-V, the factors are set to the `RegClassWeight` which is used to track register pressure. The values of `RegClassWeight` happen to be the number of register units. I believe all of the targets with compounded registers can benefit from this change, but only RISC-V is customized in this patch since it has widely been agreed to do so. The other targets need more performance data to go further. Partially fixes #113489.
This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
Use nonstatic member instead. This requires explicit conversions, but many will go away as we continue converting unsigned to Register. In a few places where it was simple, I changed unsigned to Register.
Use the nonstatic member instead. I'm pretty sure the code in SPRIV is a layering violation. MC layer files are using a CodeGen header.
In the problematic situation fixed in 61e556d2bdf3fa0a10dbaadd2dd03d01c341bd27, shouldRewriteCopySrc is called with identical register class arguments, but one has a subregister index. This was very surprising to me, and it probably shouldn't be valid for it to occur. It happens in cases with uncoalescable copies where the register class changes, and further up the chain there is a subregister operand. We could possibly just skip over uncoalsecable instructions in the chain rather than letting this query deal with it (or pre-filter the obvious subreg with same class case). The generic implementation is supposed to account for checking for valid subregisters by checking getMatchingSuperRegClass already, but that was bypassed by the early exit for exact class match. Also adds a reduced mir test demonstrating the exact problematic case.
Here we add two methods `getCommonMinimalPhysRegClass` and a LLT version `getCommonMinimalPhysRegClassLLT`, which return the most sub register class of the right type that contains these two input registers. We don't overload the `getMinimalPhysRegClass` as there will be ambiguities. We use it to simplify some code in RISC-V target.