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<title>llvm-project.git/llvm/lib/CodeGen/TargetLoweringBase.cpp, branch users/meinersbur/flang_runtime_split-headers</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[GISel] Remove unused DataLayout operand from getApproximateEVTForLLT (#119833)</title>
<updated>2024-12-13T17:09:20+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-12-13T17:09:20+00:00</published>
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<entry>
<title>[TargetLowering] Return Align from getByValTypeAlignment (NFC) (#119233)</title>
<updated>2024-12-09T20:39:19+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2024-12-09T20:39:19+00:00</published>
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<entry>
<title>[X86][BF16] Add libcall for FP128 -&gt; BF16 (#115825)</title>
<updated>2024-11-12T07:54:09+00:00</updated>
<author>
<name>Feng Zou</name>
<email>feng.zou@intel.com</email>
</author>
<published>2024-11-12T07:54:09+00:00</published>
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<id>28e4aad45a64ec893c02f21b9c2afe7efe5f4a2a</id>
<content type='text'>
This is to fix #115710.</content>
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<pre>
This is to fix #115710.</pre>
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<entry>
<title>SafeStack: Respect alloca addrspace (#112536)</title>
<updated>2024-11-05T01:51:30+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-11-05T01:51:30+00:00</published>
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<id>ea859005b5ddb14548b9dc5b94d54d78754f5918</id>
<content type='text'>
Just insert addrspacecast in cases where the alloca uses a
different address space, since I don't know what else you
could possibly do.</content>
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Just insert addrspacecast in cases where the alloca uses a
different address space, since I don't know what else you
could possibly do.</pre>
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</content>
</entry>
<entry>
<title>[IR] Add `llvm.sincos` intrinsic (#109825)</title>
<updated>2024-10-29T10:52:20+00:00</updated>
<author>
<name>Benjamin Maxwell</name>
<email>benjamin.maxwell@arm.com</email>
</author>
<published>2024-10-29T10:52:20+00:00</published>
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<id>c3260c65e86ac363aa3a39f084db66a8a1d1af7d</id>
<content type='text'>
This adds the `llvm.sincos` intrinsic, legalization, and lowering.

The `llvm.sincos` intrinsic takes a floating-point value and returns
both the sine and cosine (as a struct).

```
declare { float, float }          @llvm.sincos.f32(float  %Val)
declare { double, double }        @llvm.sincos.f64(double %Val)
declare { x86_fp80, x86_fp80 }    @llvm.sincos.f80(x86_fp80  %Val)
declare { fp128, fp128 }          @llvm.sincos.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 }  @llvm.sincos.ppcf128(ppc_fp128  %Val)
declare { &lt;4 x float&gt;, &lt;4 x float&gt; } @llvm.sincos.v4f32(&lt;4 x float&gt;  %Val)
```

The lowering is built on top of the existing FSINCOS ISD node, with
additional type legalization to allow for f16, f128, and vector values.</content>
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<pre>
This adds the `llvm.sincos` intrinsic, legalization, and lowering.

The `llvm.sincos` intrinsic takes a floating-point value and returns
both the sine and cosine (as a struct).

```
declare { float, float }          @llvm.sincos.f32(float  %Val)
declare { double, double }        @llvm.sincos.f64(double %Val)
declare { x86_fp80, x86_fp80 }    @llvm.sincos.f80(x86_fp80  %Val)
declare { fp128, fp128 }          @llvm.sincos.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 }  @llvm.sincos.ppcf128(ppc_fp128  %Val)
declare { &lt;4 x float&gt;, &lt;4 x float&gt; } @llvm.sincos.v4f32(&lt;4 x float&gt;  %Val)
```

The lowering is built on top of the existing FSINCOS ISD node, with
additional type legalization to allow for f16, f128, and vector values.</pre>
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</content>
</entry>
<entry>
<title>Check hasOptSize() in shouldOptimizeForSize() (#112626)</title>
<updated>2024-10-28T16:45:03+00:00</updated>
<author>
<name>Ellis Hoag</name>
<email>ellis.sparky.hoag@gmail.com</email>
</author>
<published>2024-10-28T16:45:03+00:00</published>
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<pre>
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<entry>
<title>[X86][CodeGen] Add base atan2 intrinsic lowering (p4) (#110760)</title>
<updated>2024-10-16T18:43:17+00:00</updated>
<author>
<name>Tex Riddell</name>
<email>texr@microsoft.com</email>
</author>
<published>2024-10-16T18:43:17+00:00</published>
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<id>875afa939df0bd3ede101447618e6d3bfc4692b3</id>
<content type='text'>
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294

Based on example PR #96222 and fix PR #101268, with some differences due
to 2-arg intrinsic and intermediate refactor (RuntimeLibCalls.cpp).

- Add llvm.experimental.constrained.atan2 - Intrinsics.td,
ConstrainedOps.def, LangRef.rst
- Add to ISDOpcodes.h and TargetSelectionDAG.td, connect to intrinsic in
BasicTTIImpl.h, and LibFunc_ in SelectionDAGBuilder.cpp
- Update LegalizeDAG.cpp, LegalizeFloatTypes.cpp, LegalizeVectorOps.cpp,
and LegalizeVectorTypes.cpp
- Update isKnownNeverNaN in SelectionDAG.cpp
- Update SelectionDAGDumper.cpp
- Update libcalls - RuntimeLibcalls.def, RuntimeLibcalls.cpp
- TargetLoweringBase.cpp - Expand for vectors, promote f16
- X86ISelLowering.cpp - Expand f80, promote f32 to f64 for MSVC

Part 4 for Implement the atan2 HLSL Function #70096.</content>
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<pre>
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294

Based on example PR #96222 and fix PR #101268, with some differences due
to 2-arg intrinsic and intermediate refactor (RuntimeLibCalls.cpp).

- Add llvm.experimental.constrained.atan2 - Intrinsics.td,
ConstrainedOps.def, LangRef.rst
- Add to ISDOpcodes.h and TargetSelectionDAG.td, connect to intrinsic in
BasicTTIImpl.h, and LibFunc_ in SelectionDAGBuilder.cpp
- Update LegalizeDAG.cpp, LegalizeFloatTypes.cpp, LegalizeVectorOps.cpp,
and LegalizeVectorTypes.cpp
- Update isKnownNeverNaN in SelectionDAG.cpp
- Update SelectionDAGDumper.cpp
- Update libcalls - RuntimeLibcalls.def, RuntimeLibcalls.cpp
- TargetLoweringBase.cpp - Expand for vectors, promote f16
- X86ISelLowering.cpp - Expand f80, promote f32 to f64 for MSVC

Part 4 for Implement the atan2 HLSL Function #70096.</pre>
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</entry>
<entry>
<title>[SDAG] Avoid creating redundant stack slots when lowering FSINCOS (#108401)</title>
<updated>2024-09-24T12:36:21+00:00</updated>
<author>
<name>Benjamin Maxwell</name>
<email>benjamin.maxwell@arm.com</email>
</author>
<published>2024-09-24T12:36:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=3073c3c2290a6d9b12fbaefa40dd22eef6312895'/>
<id>3073c3c2290a6d9b12fbaefa40dd22eef6312895</id>
<content type='text'>
When lowering `FSINCOS` to a library call (that takes output pointers)
we can avoid creating new stack allocations if the results of the
`FSINCOS` are being stored. Instead, we can take the destination
pointers from the stores and pass those to the library call.

---

Note: As a NFC this also adds (and uses) `RTLIB::getFSINCOS()`.</content>
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When lowering `FSINCOS` to a library call (that takes output pointers)
we can avoid creating new stack allocations if the results of the
`FSINCOS` are being stored. Instead, we can take the destination
pointers from the stores and pass those to the library call.

---

Note: As a NFC this also adds (and uses) `RTLIB::getFSINCOS()`.</pre>
</div>
</content>
</entry>
<entry>
<title>Reland "[X86][BF16] Add libcall for F80 -&gt; BF16 (#109116)" (#109143)</title>
<updated>2024-09-19T07:39:07+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-09-19T07:39:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c18be32185ca10e55bdef0f2d43629ccfb7e89eb'/>
<id>c18be32185ca10e55bdef0f2d43629ccfb7e89eb</id>
<content type='text'>
This reverts commit ababfee78714313a0cad87591b819f0944b90d09.

Add X86 FP80 check.</content>
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<pre>
This reverts commit ababfee78714313a0cad87591b819f0944b90d09.

Add X86 FP80 check.</pre>
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</content>
</entry>
<entry>
<title>Revert "[X86][BF16] Add libcall for F80 -&gt; BF16" (#109140)</title>
<updated>2024-09-18T13:35:38+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-09-18T13:35:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a10c9f994be143e2ac63918aa495bc2aeb3ffb48'/>
<id>a10c9f994be143e2ac63918aa495bc2aeb3ffb48</id>
<content type='text'>
Reverts llvm/llvm-project#109116</content>
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Reverts llvm/llvm-project#109116</pre>
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