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<title>llvm-project.git/llvm/lib/CodeGen/SelectionDAG, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[DAG] combineVSelectWithAllOnesOrZeros - reusing existing VT. NFC.</title>
<updated>2025-07-03T09:57:55+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-03T09:57:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c79fcfee4125dd0ad50b441517c04c55000dc7e9'/>
<id>c79fcfee4125dd0ad50b441517c04c55000dc7e9</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[SDAG] Prefer scalar for prefix of vector GEP expansion (#146719)</title>
<updated>2025-07-03T01:16:27+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-07-03T01:16:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=220a00239696257a02fe625a4819fcd038e9dd07'/>
<id>220a00239696257a02fe625a4819fcd038e9dd07</id>
<content type='text'>
When generating SDAG for a getelementptr with a vector result, we were
previously generating splats for each scalar operand. This essentially
has the effect of aggressively vectorizing the sequence, and leaving it
later combines to scalarize if profitable.

Instead, we can keep the accumulating address as a scalar for as long as
the prefix of operands allows before lazily converting to vector on the
first vector operand. This both better fits hardware which frequently
has a scalar base on the scatter/gather instructions, and reduces the
addressing cost even when not as otherwise we end up with a scalar to
vector domain crossing for each scalar operand.

Note that constant splat offsets are treated as scalar for the above,
and only variable offsets can force a conversion to vector.

---------

Co-authored-by: Craig Topper &lt;craig.topper@sifive.com&gt;</content>
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<pre>
When generating SDAG for a getelementptr with a vector result, we were
previously generating splats for each scalar operand. This essentially
has the effect of aggressively vectorizing the sequence, and leaving it
later combines to scalarize if profitable.

Instead, we can keep the accumulating address as a scalar for as long as
the prefix of operands allows before lazily converting to vector on the
first vector operand. This both better fits hardware which frequently
has a scalar base on the scatter/gather instructions, and reduces the
addressing cost even when not as otherwise we end up with a scalar to
vector domain crossing for each scalar operand.

Note that constant splat offsets are treated as scalar for the above,
and only variable offsets can force a conversion to vector.

---------

Co-authored-by: Craig Topper &lt;craig.topper@sifive.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)</title>
<updated>2025-07-02T16:44:54+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-07-02T16:44:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b62826cc054cfff75f2b5c83b980f1e12fc25e3a'/>
<id>b62826cc054cfff75f2b5c83b980f1e12fc25e3a</id>
<content type='text'>
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.</content>
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<pre>
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.</pre>
</div>
</content>
</entry>
<entry>
<title>[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (#145298)</title>
<updated>2025-07-02T14:07:48+00:00</updated>
<author>
<name>woruyu</name>
<email>99597449+woruyu@users.noreply.github.com</email>
</author>
<published>2025-07-02T14:07:48+00:00</published>
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<id>bbcebec3af5ac473f5d3557683f18a79a4b12ab5</id>
<content type='text'>
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -&gt; andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) &amp; x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</content>
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<pre>
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -&gt; andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) &amp; x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</pre>
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</content>
</entry>
<entry>
<title>[DAG] visitFREEZE - always allow freezing multiple operands (#145939)</title>
<updated>2025-07-02T10:28:37+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-02T10:28:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=38200e94f1428b586dc1778133120541e65c20b5'/>
<id>38200e94f1428b586dc1778133120541e65c20b5</id>
<content type='text'>
Always try to fold freeze(op(....)) -&gt; op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.</content>
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<pre>
Always try to fold freeze(op(....)) -&gt; op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Fix NaN regression in fma dag-combine. (#146592)</title>
<updated>2025-07-01T22:10:30+00:00</updated>
<author>
<name>James Y Knight</name>
<email>jyknight@google.com</email>
</author>
<published>2025-07-01T22:10:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ae2104897c7d9f887c415b07fb2662486082b248'/>
<id>ae2104897c7d9f887c415b07fb2662486082b248</id>
<content type='text'>
After 901e1390c9778a191256335d37802bc631c2d183 (#127770), the DAG
combine would transform `fma(x, 0.0, 1.0)` into `1.0` if
`-fp-contract=fast` was enabled, in addition to when 'x' is marked
nnan/ninf.

It's only valid in the latter case, not the former, so delete the extra
condition.</content>
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<pre>
After 901e1390c9778a191256335d37802bc631c2d183 (#127770), the DAG
combine would transform `fma(x, 0.0, 1.0)` into `1.0` if
`-fp-contract=fast` was enabled, in addition to when 'x' is marked
nnan/ninf.

It's only valid in the latter case, not the former, so delete the extra
condition.</pre>
</div>
</content>
</entry>
<entry>
<title>[DAG] canCreateUndefOrPoison - remove isGuaranteedNotToBeUndefOrPoison check for insert/extract vector element indices (#146514)</title>
<updated>2025-07-01T13:01:54+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T13:01:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=72f87d2d69b2a735f6a68e7ee53fa9a7597b6b3a'/>
<id>72f87d2d69b2a735f6a68e7ee53fa9a7597b6b3a</id>
<content type='text'>
No longer necessary now that #146490 has landed</content>
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<pre>
No longer necessary now that #146490 has landed</pre>
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</entry>
<entry>
<title>[DAG] canCreateUndefOrPoison - remove isGuaranteedNotToBeUndefOrPoison check for shift nodes (#146502)</title>
<updated>2025-07-01T11:44:59+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T11:44:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=89fe429262933ee7fcadc717c376e7fad8a48157'/>
<id>89fe429262933ee7fcadc717c376e7fad8a48157</id>
<content type='text'>
No longer necessary now that #146490 has landed - we still have the test coverage from #94145 that covers this.</content>
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<pre>
No longer necessary now that #146490 has landed - we still have the test coverage from #94145 that covers this.</pre>
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</entry>
<entry>
<title>[DAG] canCreateUndefOrPoison - add handling for CTTZ/CTLZ_ZERO_UNDEF nodes (#146501)</title>
<updated>2025-07-01T11:44:45+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T11:44:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=56841565db77af6eb668b59add3cb1d0f38875e8'/>
<id>56841565db77af6eb668b59add3cb1d0f38875e8</id>
<content type='text'>
CTTZ/CTLZ_ZERO_UNDEF nodes can only create poison if the source value is zero - so check with isKnownNeverZero

Pulled out of #146361 and reapplied now that #146490 has landed.</content>
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<pre>
CTTZ/CTLZ_ZERO_UNDEF nodes can only create poison if the source value is zero - so check with isKnownNeverZero

Pulled out of #146361 and reapplied now that #146490 has landed.</pre>
</div>
</content>
</entry>
<entry>
<title>[DAG] canCreateUndefOrPoison - explicitly state the AssertSext/Zext/Align/NoFPClass can create poison. NFC. (#146493)</title>
<updated>2025-07-01T10:31:47+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T10:31:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a97826a13b7cc5a56e7e87066d3f976ae6aef938'/>
<id>a97826a13b7cc5a56e7e87066d3f976ae6aef938</id>
<content type='text'>
This keeps getting forgotten (e.g. #66603) - so make a point of adding
it here to make it clear instead of relying on the implicit default of
returning true.</content>
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<pre>
This keeps getting forgotten (e.g. #66603) - so make a point of adding
it here to make it clear instead of relying on the implicit default of
returning true.</pre>
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</content>
</entry>
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