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<title>llvm-project.git/llvm/lib/CodeGen/SelectionDAG, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit truncation exists (#169022)</title>
<updated>2025-11-21T19:33:53+00:00</updated>
<author>
<name>Hongyu Chen</name>
<email>xxs_chy@outlook.com</email>
</author>
<published>2025-11-21T19:33:53+00:00</published>
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<id>3fec26e3294ae0f276ff08fd810850421444588c</id>
<content type='text'>
Fixes #169017</content>
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<pre>
Fixes #169017</pre>
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</entry>
<entry>
<title>[DAGCombiner] Remove unneeded m_BitReverse from visitBITREVERSE. NFC (#168918)</title>
<updated>2025-11-20T18:20:47+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-11-20T18:20:47+00:00</published>
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<id>01e5e4fd001c960e197ac377cd06ea177b320964</id>
<content type='text'>
We already know we're looking at BITREVERSE, we can match on the source
operand.</content>
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<pre>
We already know we're looking at BITREVERSE, we can match on the source
operand.</pre>
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</content>
</entry>
<entry>
<title>Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)</title>
<updated>2025-11-20T17:13:46+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-20T17:13:46+00:00</published>
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<id>0e1cb2de90aafa1d5dbd46fc9e6c4e743700fa8b</id>
<content type='text'>
This reverts commit 6d5f87fc4284c4c22512778afaf7f2ba9326ba7b.

Previously this failed due to treating the unknown MachineMemOperand
value as known uniform.</content>
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<pre>
This reverts commit 6d5f87fc4284c4c22512778afaf7f2ba9326ba7b.

Previously this failed due to treating the unknown MachineMemOperand
value as known uniform.</pre>
</div>
</content>
</entry>
<entry>
<title>[SDAG] Fix whitespace errors (NFC) (#168897)</title>
<updated>2025-11-20T16:44:31+00:00</updated>
<author>
<name>Ramkumar Ramachandra</name>
<email>ramkumar.ramachandra@codasip.com</email>
</author>
<published>2025-11-20T16:44:31+00:00</published>
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<id>602fa0c7ce4282be916613f5d056adaff11a3900</id>
<content type='text'>
To make life easier for future contributors. Note that formatting
changes are due to git clang-format on the touched whitespace-error
lines.</content>
<content type='xhtml'>
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<pre>
To make life easier for future contributors. Note that formatting
changes are due to git clang-format on the touched whitespace-error
lines.</pre>
</div>
</content>
</entry>
<entry>
<title>DAG: Fix constructing a temporary TargetTransformInfo instance (#168480)</title>
<updated>2025-11-20T06:19:23+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-20T06:19:23+00:00</published>
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<id>db20a7f2bcec85490e6ff5c998a948ccbe88ae46</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>DAG: Use poison for some vector result widening (#168290)</title>
<updated>2025-11-19T21:49:43+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-19T21:49:43+00:00</published>
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<id>253ed524365e20309e0f615415c9433bd9bda44d</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)</title>
<updated>2025-11-19T19:18:13+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-19T19:18:13+00:00</published>
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<id>a757c4e74e6a3130c708b26903d5117a9279bef8</id>
<content type='text'>
Currently LibcallLoweringInfo is defined inside of TargetLowering,
which is owned by the subtarget. Pass in the subtarget so we can
construct LibcallLoweringInfo with the subtarget. This is a temporary
step that should be revertable in the future, after LibcallLoweringInfo
is moved out of TargetLowering.</content>
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<pre>
Currently LibcallLoweringInfo is defined inside of TargetLowering,
which is owned by the subtarget. Pass in the subtarget so we can
construct LibcallLoweringInfo with the subtarget. This is a temporary
step that should be revertable in the future, after LibcallLoweringInfo
is moved out of TargetLowering.</pre>
</div>
</content>
</entry>
<entry>
<title>DAG: Use poison when splitting vector_shuffle results (#168176)</title>
<updated>2025-11-19T17:27:08+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-19T17:27:08+00:00</published>
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<id>0b921f52cc9313b89ca8fe2707d90cb1c2809387</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[DAG] Update canCreateUndefOrPoison to handle ISD::VECTOR_COMPRESS (#168010)</title>
<updated>2025-11-19T10:21:05+00:00</updated>
<author>
<name>陈子昂</name>
<email>121872494+Michael-Chen-NJU@users.noreply.github.com</email>
</author>
<published>2025-11-19T10:21:05+00:00</published>
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<id>e38529ddbb11918f854ee457b46a6dc190167029</id>
<content type='text'>
Fixes #167710
</content>
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<pre>
Fixes #167710
</pre>
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</content>
</entry>
<entry>
<title>[RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745)</title>
<updated>2025-11-18T19:13:54+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-11-18T19:13:54+00:00</published>
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<id>96e58b83a3aa681cbf5b8288c3012d5d5d20398c</id>
<content type='text'>
If vector-unaligned-mem support is not enabled, we should not generate
loads/stores that are not aligned to their element size.

We already do this for non-VP vector loads/stores.

This code has been in our downstream for about a year and a half after
finding the vectorizer generating misaligned loads/stores. I don't think
that is unique to our downstream.

Doing this for masked vp.load/store requires widening the mask as well
which is harder to do.

NOTE: Because we have to scale the VL, this will introduce additional
vsetvli and the VL optimizer will not be effective at optimizing any
arithmetic that is consumed by the store.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If vector-unaligned-mem support is not enabled, we should not generate
loads/stores that are not aligned to their element size.

We already do this for non-VP vector loads/stores.

This code has been in our downstream for about a year and a half after
finding the vectorizer generating misaligned loads/stores. I don't think
that is unique to our downstream.

Doing this for masked vp.load/store requires widening the mask as well
which is harder to do.

NOTE: Because we have to scale the VL, this will introduce additional
vsetvli and the VL optimizer will not be effective at optimizing any
arithmetic that is consumed by the store.</pre>
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</content>
</entry>
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