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<title>llvm-project.git/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[TargetLowering] Fold (a | b) ==/!= b -&gt; (a &amp; ~b) ==/!= 0 when and-not exists (#145368)</title>
<updated>2025-06-27T13:47:52+00:00</updated>
<author>
<name>AZero13</name>
<email>gfunni234@gmail.com</email>
</author>
<published>2025-06-27T13:47:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dcea5f1f38eba03aa035375a7cd8d4eb0413934e'/>
<id>dcea5f1f38eba03aa035375a7cd8d4eb0413934e</id>
<content type='text'>
This is especially helpful for AArch64, which simplifies ands + cmp to tst.
Alive2: https://alive2.llvm.org/ce/z/LLgcJJ

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</content>
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<pre>
This is especially helpful for AArch64, which simplifies ands + cmp to tst.
Alive2: https://alive2.llvm.org/ce/z/LLgcJJ

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</pre>
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</content>
</entry>
<entry>
<title>DAG: Check libcall function is supported before emission (#144314)</title>
<updated>2025-06-27T09:09:04+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-27T09:09:04+00:00</published>
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<pre>
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</entry>
<entry>
<title>[SelectionDAG] Fold undemanded operand to UNDEF for VECTOR_SHUFFLE (#145524)</title>
<updated>2025-06-25T14:05:54+00:00</updated>
<author>
<name>Björn Pettersson</name>
<email>bjorn.a.pettersson@ericsson.com</email>
</author>
<published>2025-06-25T14:05:54+00:00</published>
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<id>fd3cc204de96728991837259ba3959dd69a235b6</id>
<content type='text'>
Always let SimplifyDemandedVectorElts fold either side of a
VECTOR_SHUFFLE to UNDEF if no elements are demanded from that side.

For a single use this could be done by SimplifyDemandedVectorElts
already, but in case the operand had multiple uses we did not eliminate
the use.</content>
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<pre>
Always let SimplifyDemandedVectorElts fold either side of a
VECTOR_SHUFFLE to UNDEF if no elements are demanded from that side.

For a single use this could be done by SimplifyDemandedVectorElts
already, but in case the operand had multiple uses we did not eliminate
the use.</pre>
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</content>
</entry>
<entry>
<title>[SelectionDAG] Handle `fneg`/`fabs`/`fcopysign` in `SimplifyDemandedBits` (#139239)</title>
<updated>2025-06-22T14:48:59+00:00</updated>
<author>
<name>Iris Shi</name>
<email>0.0@owo.li</email>
</author>
<published>2025-06-22T14:48:59+00:00</published>
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<id>f2eb5d416ed1e539b215aa0bab46b8e8a98f1eec</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[LLVM][CodeGen][SVE] Add isel for bfloat unordered reductions. (#143540)</title>
<updated>2025-06-20T10:46:25+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2025-06-20T10:46:25+00:00</published>
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The omissions are VECREDUCE_SEQ_* and MUL. The former goes down a
different code path and the latter is unsupported across all element types.</content>
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<pre>
The omissions are VECREDUCE_SEQ_* and MUL. The former goes down a
different code path and the latter is unsupported across all element types.</pre>
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</content>
</entry>
<entry>
<title>DAG: Move soft float predicate management into RuntimeLibcalls (#142905)</title>
<updated>2025-06-17T00:42:53+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-17T00:42:53+00:00</published>
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<id>97bfb936af4077e8cb6c75664231f27a9989d563</id>
<content type='text'>
Work towards making RuntimeLibcalls the centralized location for
all libcall information. This requires changing the encoding from
tracking the ISD::CondCode to using CmpInst::Predicate.</content>
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<pre>
Work towards making RuntimeLibcalls the centralized location for
all libcall information. This requires changing the encoding from
tracking the ISD::CondCode to using CmpInst::Predicate.</pre>
</div>
</content>
</entry>
<entry>
<title>DAG: Assert fcmp uno runtime calls are boolean values (#142898)</title>
<updated>2025-06-10T01:46:29+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-10T01:46:29+00:00</published>
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<id>505c550e4c12d24093f46afaa35819ab2a1a530a</id>
<content type='text'>
This saves 2 instructions in the ARM soft float case for fcmp ueq.

This code is written in an confusingly overly general way. The point
of getCmpLibcallCC is to express that the compiler-rt implementations
of the FP compares are different aliases around functions which may
return -1 in some cases. This does not apply to the call for unordered,
which returns a normal boolean.

Also stop overriding the default value for the unordered compare for ARM.
This was setting it to the same value as the default, which is now assumed.</content>
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<pre>
This saves 2 instructions in the ARM soft float case for fcmp ueq.

This code is written in an confusingly overly general way. The point
of getCmpLibcallCC is to express that the compiler-rt implementations
of the FP compares are different aliases around functions which may
return -1 in some cases. This does not apply to the call for unordered,
which returns a normal boolean.

Also stop overriding the default value for the unordered compare for ARM.
This was setting it to the same value as the default, which is now assumed.</pre>
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</content>
</entry>
<entry>
<title>[SDAG] Add partial_reduce_sumla node (#141267)</title>
<updated>2025-06-09T14:17:45+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-06-09T14:17:45+00:00</published>
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<id>939666380fba5d6db3d224fc358fd3e0f40a9b53</id>
<content type='text'>
We have recently added the partial_reduce_smla and partial_reduce_umla
nodes to represent Acc += ext(b) * ext(b) where the two extends have to
have the same source type, and have the same extend kind.

For riscv64 w/zvqdotq, we have the vqdot and vqdotu instructions which
correspond to the existing nodes, but we also have vqdotsu which
represents the case where the two extends are sign and zero respective
(i.e. not the same type of extend).

This patch adds a partial_reduce_sumla node which has sign extension for
A, and zero extension for B. The addition is somewhat mechanical.</content>
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<pre>
We have recently added the partial_reduce_smla and partial_reduce_umla
nodes to represent Acc += ext(b) * ext(b) where the two extends have to
have the same source type, and have the same extend kind.

For riscv64 w/zvqdotq, we have the vqdot and vqdotu instructions which
correspond to the existing nodes, but we also have vqdotsu which
represents the case where the two extends are sign and zero respective
(i.e. not the same type of extend).

This patch adds a partial_reduce_sumla node which has sign extension for
A, and zero extension for B. The addition is somewhat mechanical.</pre>
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</content>
</entry>
<entry>
<title>Revert "[SDAG] Fix fmaximum legalization errors (#142170)"</title>
<updated>2025-06-04T12:35:30+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-06-04T12:35:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d74831efeb1d32213ca824d23283606eb870d8fd'/>
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<content type='text'>
This reverts commit 58cc1675ec7b4aa5bc2dab56180cb7af1b23ade5.

I also made the incorrect assumption that we know both values are
+/-0.0 here as well. Revert for now.
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<pre>
This reverts commit 58cc1675ec7b4aa5bc2dab56180cb7af1b23ade5.

I also made the incorrect assumption that we know both values are
+/-0.0 here as well. Revert for now.
</pre>
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</content>
</entry>
<entry>
<title>Revert "[SelectionDAG] Avoid one comparison when legalizing fmaximum (#142732)"</title>
<updated>2025-06-04T12:22:19+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-06-04T12:20:42+00:00</published>
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<id>42605b8aa31b82d8f3ba15bdca11ff3d52527a5e</id>
<content type='text'>
This reverts commit 54da543a14da6dd0e594875241494949cb659b08.

I made a logic error here with the assumption that both values
are known to be +/-0.0.
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<pre>
This reverts commit 54da543a14da6dd0e594875241494949cb659b08.

I made a logic error here with the assumption that both values
are known to be +/-0.0.
</pre>
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