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<title>llvm-project.git/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)</title>
<updated>2025-11-19T19:18:13+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-19T19:18:13+00:00</published>
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<id>a757c4e74e6a3130c708b26903d5117a9279bef8</id>
<content type='text'>
Currently LibcallLoweringInfo is defined inside of TargetLowering,
which is owned by the subtarget. Pass in the subtarget so we can
construct LibcallLoweringInfo with the subtarget. This is a temporary
step that should be revertable in the future, after LibcallLoweringInfo
is moved out of TargetLowering.</content>
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<pre>
Currently LibcallLoweringInfo is defined inside of TargetLowering,
which is owned by the subtarget. Pass in the subtarget so we can
construct LibcallLoweringInfo with the subtarget. This is a temporary
step that should be revertable in the future, after LibcallLoweringInfo
is moved out of TargetLowering.</pre>
</div>
</content>
</entry>
<entry>
<title>DAG: Move expandMultipleResultFPLibCall to TargetLowering (NFC) (#166988)</title>
<updated>2025-11-12T03:50:33+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-12T03:50:33+00:00</published>
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<id>c5aace42360184a75323d8fab3a26f0a1d8ba5e7</id>
<content type='text'>
This kind of helper is higher level and not general enough to go
directly in SelectionDAG. Most similar utilities are in TargetLowering.</content>
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<pre>
This kind of helper is higher level and not general enough to go
directly in SelectionDAG. Most similar utilities are in TargetLowering.</pre>
</div>
</content>
</entry>
<entry>
<title>Add `llvm.vector.partial.reduce.fadd` intrinsic (#159776)</title>
<updated>2025-11-07T15:36:54+00:00</updated>
<author>
<name>Damian Heaton</name>
<email>Damian.Heaton@arm.com</email>
</author>
<published>2025-11-07T15:36:54+00:00</published>
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<id>70f4b596cf453369ce4111c23e7e93633e5fe4b1</id>
<content type='text'>
With this intrinsic, and supporting SelectionDAG nodes, we can better
make use of instructions such as AArch64's `FDOT`.</content>
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<pre>
With this intrinsic, and supporting SelectionDAG nodes, we can better
make use of instructions such as AArch64's `FDOT`.</pre>
</div>
</content>
</entry>
<entry>
<title>[SDAG] Set InBounds when when computing offsets into memory objects (#165425)</title>
<updated>2025-10-31T10:27:55+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-10-31T10:27:55+00:00</published>
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<id>8ea447b4c4b007ea1c736f71e569fda621f4fdc8</id>
<content type='text'>
When a load or store accesses N bytes starting from a pointer P, and we want to
compute an offset pointer within these N bytes after P, we know that the
arithmetic to add the offset must be inbounds. This is for example relevant
when legalizing too-wide memory accesses, when lowering memcpy&amp;Co., or when
optimizing "vector-load -&gt; extractelement" into an offset load.

For SWDEV-516125.</content>
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<pre>
When a load or store accesses N bytes starting from a pointer P, and we want to
compute an offset pointer within these N bytes after P, we know that the
arithmetic to add the offset must be inbounds. This is for example relevant
when legalizing too-wide memory accesses, when lowering memcpy&amp;Co., or when
optimizing "vector-load -&gt; extractelement" into an offset load.

For SWDEV-516125.</pre>
</div>
</content>
</entry>
<entry>
<title>[DAGCombine] Improve bswap lowering for machines that support bit rotates (#164848)</title>
<updated>2025-10-25T17:17:15+00:00</updated>
<author>
<name>AZero13</name>
<email>gfunni234@gmail.com</email>
</author>
<published>2025-10-25T17:17:15+00:00</published>
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<id>5d0f1591f8b91ac7919910c4e3e9614a8804c02a</id>
<content type='text'>
Source: Hacker's delight.</content>
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<pre>
Source: Hacker's delight.</pre>
</div>
</content>
</entry>
<entry>
<title>Wasm fmuladd relaxed (#163177)</title>
<updated>2025-10-13T15:50:53+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2025-10-13T15:50:53+00:00</published>
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<id>1820102167a5ace14a5c1f79d11d5eb4cce93001</id>
<content type='text'>
Reland #161355, after fixing up the cross-projects-tests for the wasm
simd intrinsics.

Original commit message:
Lower v4f32 and v2f64 fmuladd calls to relaxed_madd instructions.
If we have FP16, then lower v8f16 fmuladds to FMA.

I've introduced an ISD node for fmuladd to maintain the rounding
ambiguity through legalization / combine / isel.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Reland #161355, after fixing up the cross-projects-tests for the wasm
simd intrinsics.

Original commit message:
Lower v4f32 and v2f64 fmuladd calls to relaxed_madd instructions.
If we have FP16, then lower v8f16 fmuladds to FMA.

I've introduced an ISD node for fmuladd to maintain the rounding
ambiguity through legalization / combine / isel.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[WebAssembly] Lower fmuladd to madd and nmadd" (#163171)</title>
<updated>2025-10-13T10:53:40+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2025-10-13T10:53:40+00:00</published>
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<id>30d3441cf082c3672cd7b8495cb8cc1d6ca2c8e0</id>
<content type='text'>
Reverts llvm/llvm-project#161355

Looks like I've broken some intrinsic code generation.</content>
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<pre>
Reverts llvm/llvm-project#161355

Looks like I've broken some intrinsic code generation.</pre>
</div>
</content>
</entry>
<entry>
<title>[WebAssembly] Lower fmuladd to madd and nmadd (#161355)</title>
<updated>2025-10-13T09:36:08+00:00</updated>
<author>
<name>Sam Parker</name>
<email>sam.parker@arm.com</email>
</author>
<published>2025-10-13T09:36:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a4eb7ea22575afa40d79475c15fc2d0ad3f4498a'/>
<id>a4eb7ea22575afa40d79475c15fc2d0ad3f4498a</id>
<content type='text'>
Lower v4f32 and v2f64 fmuladd calls to relaxed_madd instructions.
If we have FP16, then lower v8f16 fmuladds to FMA.

I've introduced an ISD node for fmuladd to maintain the rounding
ambiguity through legalization / combine / isel.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Lower v4f32 and v2f64 fmuladd calls to relaxed_madd instructions.
If we have FP16, then lower v8f16 fmuladds to FMA.

I've introduced an ISD node for fmuladd to maintain the rounding
ambiguity through legalization / combine / isel.</pre>
</div>
</content>
</entry>
<entry>
<title>[TargetLowering] Remove NoSignedZerosFPMath uses (#160975)</title>
<updated>2025-09-29T06:33:56+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2025-09-29T06:33:56+00:00</published>
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<id>b0a755b2bfac0a82383dcc31eca82d9e132f1afc</id>
<content type='text'>
Remove NoSignedZerosFPMath in TargetLowering part, users should always
use instruction level fast math flags.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove NoSignedZerosFPMath in TargetLowering part, users should always
use instruction level fast math flags.</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Improve v2f16 maximumnum expansion (#160723)</title>
<updated>2025-09-26T10:37:29+00:00</updated>
<author>
<name>Lewis Crawford</name>
<email>lcrawford@nvidia.com</email>
</author>
<published>2025-09-26T10:37:29+00:00</published>
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<id>a27baf9c96a484312a1a32df1e552bcce7a610d1</id>
<content type='text'>
On targets where f32 maximumnum is legal, but maximumnum on vectors of
smaller types is not legal (e.g. v2f16), try unrolling the vector first
as part of the expansion.

Only fall back to expanding the full maximumnum computation into
compares + selects if maximumnum on the scalar element type cannot be
supported.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On targets where f32 maximumnum is legal, but maximumnum on vectors of
smaller types is not legal (e.g. v2f16), try unrolling the vector first
as part of the expansion.

Only fall back to expanding the full maximumnum computation into
compares + selects if maximumnum on the scalar element type cannot be
supported.</pre>
</div>
</content>
</entry>
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