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<title>llvm-project.git/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[CodeGen] Construct SmallVector with ArrayRef (NFC) (#143391)</title>
<updated>2025-06-09T19:45:52+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-06-09T19:45:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=60cd76bc34901645654b5bbbc9e06cf267c1f887'/>
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<pre>
</pre>
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</entry>
<entry>
<title>RuntimeLibcalls: Rename fminimum_num/fmaximum_num enums (#143078)</title>
<updated>2025-06-06T07:23:26+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-06T07:23:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b2266d6d79fc1dae145cef0de7358eb9e304075c'/>
<id>b2266d6d79fc1dae145cef0de7358eb9e304075c</id>
<content type='text'>
Add the underscore to match the libm spelling</content>
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<pre>
Add the underscore to match the libm spelling</pre>
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</content>
</entry>
<entry>
<title>Revert "[SDAG] Fix fmaximum legalization errors (#142170)"</title>
<updated>2025-06-04T12:35:30+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-06-04T12:35:21+00:00</published>
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<id>d74831efeb1d32213ca824d23283606eb870d8fd</id>
<content type='text'>
This reverts commit 58cc1675ec7b4aa5bc2dab56180cb7af1b23ade5.

I also made the incorrect assumption that we know both values are
+/-0.0 here as well. Revert for now.
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<pre>
This reverts commit 58cc1675ec7b4aa5bc2dab56180cb7af1b23ade5.

I also made the incorrect assumption that we know both values are
+/-0.0 here as well. Revert for now.
</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG][AArch64] Legalize power of 2 vector.[de]interleaveN (#141513)</title>
<updated>2025-06-03T11:05:44+00:00</updated>
<author>
<name>Luke Lau</name>
<email>luke@igalia.com</email>
</author>
<published>2025-06-03T11:05:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9a2d4d176ad290eb556f27a990880acad99cc163'/>
<id>9a2d4d176ad290eb556f27a990880acad99cc163</id>
<content type='text'>
After https://github.com/llvm/llvm-project/pull/139893, we now have
[de]interleave intrinsics for factors 2-8 inclusive, with the plan to
eventually get the loop vectorizer to emit a single intrinsic for these
factors instead of recursively deinterleaving (to support scalable
non-power-of-2 factors and to remove the complexity in the interleaved
access pass).

AArch64 currently supports scalable interleaved groups of factors 2 and
4 from the loop vectorizer. For factor 4 this is currently emitted as a
series of recursive [de]interleaves, and normally converted to a target
intrinsic in the interleaved access pass.

However if for some reason the interleaved access pass doesn't catch it,
the [de]interleave4 intrinsic will need to be lowered by the backend.

This patch legalizes the node and any other power-of-2 factor to smaller
factors, so if a target can lower [de]interleave2 it should be able to
handle this without crashing.

Factor 3 will probably be more complicated to lower so I've left it out
for now. We can disable it in the AArch64 cost model when implementing
the loop vectorizer changes.</content>
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<pre>
After https://github.com/llvm/llvm-project/pull/139893, we now have
[de]interleave intrinsics for factors 2-8 inclusive, with the plan to
eventually get the loop vectorizer to emit a single intrinsic for these
factors instead of recursively deinterleaving (to support scalable
non-power-of-2 factors and to remove the complexity in the interleaved
access pass).

AArch64 currently supports scalable interleaved groups of factors 2 and
4 from the loop vectorizer. For factor 4 this is currently emitted as a
series of recursive [de]interleaves, and normally converted to a target
intrinsic in the interleaved access pass.

However if for some reason the interleaved access pass doesn't catch it,
the [de]interleave4 intrinsic will need to be lowered by the backend.

This patch legalizes the node and any other power-of-2 factor to smaller
factors, so if a target can lower [de]interleave2 it should be able to
handle this without crashing.

Factor 3 will probably be more complicated to lower so I've left it out
for now. We can disable it in the AArch64 cost model when implementing
the loop vectorizer changes.</pre>
</div>
</content>
</entry>
<entry>
<title>[SDAG] Fix fmaximum legalization errors (#142170)</title>
<updated>2025-06-02T08:14:33+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-06-02T08:14:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=58cc1675ec7b4aa5bc2dab56180cb7af1b23ade5'/>
<id>58cc1675ec7b4aa5bc2dab56180cb7af1b23ade5</id>
<content type='text'>
FMAXIMUM is currently legalized via IS_FPCLASS for the signed zero
handling. This is problematic, because it assumes the equivalent integer
type is legal. Many targets have legal fp128, but illegal i128, so this
results in legalization failures.

Fix this by replacing IS_FPCLASS with checking the bitcast to integer
instead. In that case it is sufficient to use any legal integer type, as
we're just interested in the sign bit. This can be obtained via a stack
temporary cast. There is existing FloatSignAsInt functionality used for
legalization of FABS and similar we can use for this purpose.

Fixes https://github.com/llvm/llvm-project/issues/139380.
Fixes https://github.com/llvm/llvm-project/issues/139381.
Fixes https://github.com/llvm/llvm-project/issues/140445.</content>
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<pre>
FMAXIMUM is currently legalized via IS_FPCLASS for the signed zero
handling. This is problematic, because it assumes the equivalent integer
type is legal. Many targets have legal fp128, but illegal i128, so this
results in legalization failures.

Fix this by replacing IS_FPCLASS with checking the bitcast to integer
instead. In that case it is sufficient to use any legal integer type, as
we're just interested in the sign bit. This can be obtained via a stack
temporary cast. There is existing FloatSignAsInt functionality used for
legalization of FABS and similar we can use for this purpose.

Fixes https://github.com/llvm/llvm-project/issues/139380.
Fixes https://github.com/llvm/llvm-project/issues/139381.
Fixes https://github.com/llvm/llvm-project/issues/140445.</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)</title>
<updated>2025-05-16T16:37:02+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-05-16T16:37:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dcd62f3674907b0d31a303b95ea5aa844ffd8238'/>
<id>dcd62f3674907b0d31a303b95ea5aa844ffd8238</id>
<content type='text'>
This matches the underlying function in MachineMemOperand and how it is
printed when BaseAlign differs from Align.</content>
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<pre>
This matches the underlying function in MachineMemOperand and how it is
printed when BaseAlign differs from Align.</pre>
</div>
</content>
</entry>
<entry>
<title>[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#101786)</title>
<updated>2025-04-23T09:43:05+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2025-04-23T09:43:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=11a3de7e98785b0df8f2010fb22c10c0590d2707'/>
<id>11a3de7e98785b0df8f2010fb22c10c0590d2707</id>
<content type='text'>
This is a reland of #99752 with the bug fixed (see test diff in the
third commit in this PR).
All `popcount` libcalls return `int`, but `ISD::CTPOP` returns the type
of the argument, which can be wider than `int`. The fix is to make DAG
legalizer pass the correct return type to `makeLibCall` and sign-extend
the result afterwards.

Original commit message:
The main change is adding CTPOP to `RuntimeLibcalls.def` to allow
targets to use LibCall action for CTPOP. DAG legalizers are changed
accordingly.

Pull Request: https://github.com/llvm/llvm-project/pull/101786
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is a reland of #99752 with the bug fixed (see test diff in the
third commit in this PR).
All `popcount` libcalls return `int`, but `ISD::CTPOP` returns the type
of the argument, which can be wider than `int`. The fix is to make DAG
legalizer pass the correct return type to `makeLibCall` and sign-extend
the result afterwards.

Original commit message:
The main change is adding CTPOP to `RuntimeLibcalls.def` to allow
targets to use LibCall action for CTPOP. DAG legalizers are changed
accordingly.

Pull Request: https://github.com/llvm/llvm-project/pull/101786
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix 'unannotated fall-through between switch labels' warning. (#136000)</title>
<updated>2025-04-16T18:25:10+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulson1@linux.ibm.com</email>
</author>
<published>2025-04-16T18:25:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e19fcb72d7fbda6a1e67c45b85b399fe69d212ad'/>
<id>e19fcb72d7fbda6a1e67c45b85b399fe69d212ad</id>
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</content>
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<pre>
</pre>
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</entry>
<entry>
<title>[SystemZ] Add support for 16-bit floating point. (#109164)</title>
<updated>2025-04-16T18:02:56+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulson1@linux.ibm.com</email>
</author>
<published>2025-04-16T18:02:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6d03f51f0c59171f1ec3c5cc5c1fe71c30956273'/>
<id>6d03f51f0c59171f1ec3c5cc5c1fe71c30956273</id>
<content type='text'>
- _Float16 is now accepted by Clang.

- The half IR type is fully handled by the backend.

- These values are passed in FP registers and converted to/from float around
  each operation.

- Compiler-rt conversion functions are now built for s390x including the missing
  extendhfdf2 which was added.

Fixes #50374</content>
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<pre>
- _Float16 is now accepted by Clang.

- The half IR type is fully handled by the backend.

- These values are passed in FP registers and converted to/from float around
  each operation.

- Compiler-rt conversion functions are now built for s390x including the missing
  extendhfdf2 which was added.

Fixes #50374</pre>
</div>
</content>
</entry>
<entry>
<title>Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (#135056)</title>
<updated>2025-04-10T15:29:14+00:00</updated>
<author>
<name>zhijian lin</name>
<email>zhijian@ca.ibm.com</email>
</author>
<published>2025-04-10T15:29:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=378ac572accc6d14ed36136f261951f8607a9169'/>
<id>378ac572accc6d14ed36136f261951f8607a9169</id>
<content type='text'>
A new ISD::POISON SDNode is introduced to represent the poison value in
the IR, replacing the previous use of ISD::UNDEF
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A new ISD::POISON SDNode is introduced to represent the poison value in
the IR, replacing the previous use of ISD::UNDEF
</pre>
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</content>
</entry>
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