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<title>llvm-project.git/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[ScheduleDAG] Allow disabling the SchedModel / Itineraries during Scheduling (#138057)</title>
<updated>2025-05-05T21:07:23+00:00</updated>
<author>
<name>Jeffrey Byrnes</name>
<email>jeffrey.byrnes@amd.com</email>
</author>
<published>2025-05-05T21:07:23+00:00</published>
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<content type='text'>
This provides the `disable-schedmodel-in-sched-mi` flag. Using this, we
will disable the SchedModel / Itineraries during scheduling. This has
the effect of not using any latency / hardware resource information for
scheduling decisions.

We have the `schedmodel` flag, but this disables the `SchedModel` for
all passes. This allows disabling only for scheduling while preserving
the behavior of other passes (e.g. MachineLICM). This is conceptually
similar to other flags like `enable-aa-sched-mi`</content>
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<pre>
This provides the `disable-schedmodel-in-sched-mi` flag. Using this, we
will disable the SchedModel / Itineraries during scheduling. This has
the effect of not using any latency / hardware resource information for
scheduling decisions.

We have the `schedmodel` flag, but this disables the `SchedModel` for
all passes. This allows disabling only for scheduling while preserving
the behavior of other passes (e.g. MachineLICM). This is conceptually
similar to other flags like `enable-aa-sched-mi`</pre>
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</content>
</entry>
<entry>
<title>[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)</title>
<updated>2025-02-01T17:40:50+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2025-02-01T17:40:50+00:00</published>
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<content type='text'>
Providing the correct operand index allows addPhysRegDataDeps to compute
the correct latency.

Pull Request: https://github.com/llvm/llvm-project/pull/123541
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<pre>
Providing the correct operand index allows addPhysRegDataDeps to compute
the correct latency.

Pull Request: https://github.com/llvm/llvm-project/pull/123541
</pre>
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</entry>
<entry>
<title>[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)</title>
<updated>2025-01-23T09:16:09+00:00</updated>
<author>
<name>Benjamin Maxwell</name>
<email>benjamin.maxwell@arm.com</email>
</author>
<published>2025-01-23T09:16:09+00:00</published>
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<content type='text'>
Once we get to SelectionDAG the IR should not be changing anymore, so we
can use BatchAAResults rather than AAResults to cache AA queries.

This should be a NFC change for targets that enable AA during codegen
(such as AArch64), but also give a nice compile-time improvement in some
cases. See:
https://github.com/llvm/llvm-project/pull/123787#issuecomment-2606797041

Note: This follows Nikita's suggestion on #123787.</content>
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<pre>
Once we get to SelectionDAG the IR should not be changing anymore, so we
can use BatchAAResults rather than AAResults to cache AA queries.

This should be a NFC change for targets that enable AA during codegen
(such as AArch64), but also give a nice compile-time improvement in some
cases. See:
https://github.com/llvm/llvm-project/pull/123787#issuecomment-2606797041

Note: This follows Nikita's suggestion on #123787.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Add target hook to isGlobalMemoryObject (#112781)</title>
<updated>2025-01-11T17:57:57+00:00</updated>
<author>
<name>Austin Kerbow</name>
<email>Austin.Kerbow@amd.com</email>
</author>
<published>2025-01-11T17:57:57+00:00</published>
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<content type='text'>
We want special handing for IGLP instructions in the scheduler but they
should still be treated like they have side effects by other passes. Add
a target hook to the ScheduleDAGInstrs DAG builder so that we have more
control over this.</content>
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<pre>
We want special handing for IGLP instructions in the scheduler but they
should still be treated like they have side effects by other passes. Add
a target hook to the ScheduleDAGInstrs DAG builder so that we have more
control over this.</pre>
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</content>
</entry>
<entry>
<title>[NFC] Remove some unnecessary semicolons</title>
<updated>2024-12-16T08:48:57+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-12-16T08:48:57+00:00</published>
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All inside LLVM_DEBUG, some of which have been cleaned up by adding block
scopes to allow them to format more nicely.
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All inside LLVM_DEBUG, some of which have been cleaned up by adding block
scopes to allow them to format more nicely.
</pre>
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</entry>
<entry>
<title>Fix typo "necessarilly"</title>
<updated>2024-11-14T17:01:17+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-11-14T17:01:17+00:00</published>
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</entry>
<entry>
<title>[NFC] Use initial-stack-allocations for more data structures (#110544)</title>
<updated>2024-09-30T22:15:18+00:00</updated>
<author>
<name>Jeremy Morse</name>
<email>jeremy.morse@sony.com</email>
</author>
<published>2024-09-30T22:15:18+00:00</published>
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<id>96f37ae45310885e09195be09d9c05e1c1dff86b</id>
<content type='text'>
This replaces some of the most frequent offenders of using a DenseMap that
cause a malloc, where the typical element-count is small enough to fit in
an initial stack allocation.

Most of these are fairly obvious, one to highlight is the collectOffset
method of GEP instructions: if there's a GEP, of course it's going to have
at least one offset, but every time we've called collectOffset we end up
calling malloc as well for the DenseMap in the MapVector.</content>
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<pre>
This replaces some of the most frequent offenders of using a DenseMap that
cause a malloc, where the typical element-count is small enough to fit in
an initial stack allocation.

Most of these are fairly obvious, one to highlight is the collectOffset
method of GEP instructions: if there's a GEP, of course it's going to have
at least one offset, but every time we've called collectOffset we end up
calling malloc as well for the DenseMap in the MapVector.</pre>
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</content>
</entry>
<entry>
<title>[llvm][CodeGen] Avoid 'raw_string_ostream::str' (NFC) (#97318)</title>
<updated>2024-07-02T01:52:37+00:00</updated>
<author>
<name>Youngsuk Kim</name>
<email>joseph942010@gmail.com</email>
</author>
<published>2024-07-02T01:52:37+00:00</published>
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<content type='text'>
Since `raw_string_ostream` doesn't own the string buffer, it is
desirable (in terms of memory safety) for users to directly reference
the string buffer rather than use `raw_string_ostream::str()`.

Work towards TODO comment to remove `raw_string_ostream::str()`.</content>
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<pre>
Since `raw_string_ostream` doesn't own the string buffer, it is
desirable (in terms of memory safety) for users to directly reference
the string buffer rather than use `raw_string_ostream::str()`.

Work towards TODO comment to remove `raw_string_ostream::str()`.</pre>
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</content>
</entry>
<entry>
<title>[AArch64] Improve scheduling latency into Bundles (#86310)</title>
<updated>2024-04-12T09:57:01+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-04-12T09:57:01+00:00</published>
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By default the scheduling info of instructions into a BUNDLE are given a
latency of 0 as they operate on the implicit register of the bundle.
This modifies that for AArch64 so that the latency is adjusted to use
the latency from the instruction in the bundle instead. This essentially
assumes that the bundled instructions are executed in a single cycle,
which for AArch64 is probably OK considering they are mostly used for
MOVPFX bundles, where this can help create slightly better scheduling
especially for in-order cores.</content>
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By default the scheduling info of instructions into a BUNDLE are given a
latency of 0 as they operate on the implicit register of the bundle.
This modifies that for AArch64 so that the latency is adjusted to use
the latency from the instruction in the bundle instead. This essentially
assumes that the bundled instructions are executed in a single cycle,
which for AArch64 is probably OK considering they are mostly used for
MOVPFX bundles, where this can help create slightly better scheduling
especially for in-order cores.</pre>
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</content>
</entry>
<entry>
<title>[SelectionDAG] Switch to LiveRegUnits (#84197)</title>
<updated>2024-03-11T07:17:39+00:00</updated>
<author>
<name>AtariDreams</name>
<email>83477269+AtariDreams@users.noreply.github.com</email>
</author>
<published>2024-03-11T07:17:39+00:00</published>
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