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<title>llvm-project.git/llvm/lib/CodeGen/RegisterScavenging.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Remove TRI arguments from stack load/store hooks (#158240)</title>
<updated>2025-11-11T00:24:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-11T00:24:39+00:00</published>
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This is directly available in TargetInstrInfo</content>
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This is directly available in TargetInstrInfo</pre>
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</entry>
<entry>
<title>[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (#140002)</title>
<updated>2025-05-22T15:07:52+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-22T15:07:52+00:00</published>
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<id>1fdf02ad5a4ca155017eea22688365a20aab077c</id>
<content type='text'>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</content>
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Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Use Register::id() to avoid implicit cast. NFC</title>
<updated>2025-03-03T06:33:26+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-03T04:48:17+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Use non-static Register::virtRegIndex() instead of static Register::virtReg2Index. NFC (#125031)</title>
<updated>2025-01-30T08:14:08+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-30T08:14:08+00:00</published>
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<id>473953a15fcf68f2a213e2fed7b47a2a690baff2</id>
<content type='text'>
These are the the ones where we already had a Register object being
used. Some places are still using unsigned which I did not convert.</content>
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These are the the ones where we already had a Register object being
used. Some places are still using unsigned which I did not convert.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Remove unused includes (NFC) (#115996)</title>
<updated>2024-11-13T07:15:06+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-13T07:15:06+00:00</published>
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<id>735ab61ac828bd61398e6847d60e308fdf2b54ec</id>
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Identified with misc-include-cleaner.</content>
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Identified with misc-include-cleaner.</pre>
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</entry>
<entry>
<title>[RegScavenger] Simplify state tracking for backwards scavenging (#71202)</title>
<updated>2023-11-08T09:49:07+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-11-08T09:49:07+00:00</published>
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<id>d5f3b3b3b188d17aa8a2227d31e8fd7611d7dfff</id>
<content type='text'>
Track the live register state immediately before, instead of after,
MBBI. This makes it simple to track the state at the start or end of a
basic block without a separate (and poorly named) Tracking flag.

This changes the API of the backward(MachineBasicBlock::iterator I)
method, which now recedes to the state just before, instead of just
after, *I. Some clients are simplified by this change.

There is one small functional change shown in the lit tests where
multiple spilled registers all need to be reloaded before the same
instruction. The reloads will now be inserted in the opposite order.
This should not affect correctness.</content>
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<pre>
Track the live register state immediately before, instead of after,
MBBI. This makes it simple to track the state at the start or end of a
basic block without a separate (and poorly named) Tracking flag.

This changes the API of the backward(MachineBasicBlock::iterator I)
method, which now recedes to the state just before, instead of just
after, *I. Some clients are simplified by this change.

There is one small functional change shown in the lit tests where
multiple spilled registers all need to be reloaded before the same
instruction. The reloads will now be inserted in the opposite order.
This should not affect correctness.</pre>
</div>
</content>
</entry>
<entry>
<title>[RegScavenger] Remove support for forwards register scavenging</title>
<updated>2023-08-04T07:52:15+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-08-03T10:50:44+00:00</published>
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<id>76cfdbe2546f6e278e5c37f5607b0fbc36086a76</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D156987
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<pre>
Differential Revision: https://reviews.llvm.org/D156987
</pre>
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</entry>
<entry>
<title>[MC] Add MCRegisterInfo::regunits for iteration over register units</title>
<updated>2023-06-16T02:39:50+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2023-05-21T01:28:33+00:00</published>
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<id>aa2d0fbc30d948dc9ce7d312ae4c56467fa57932</id>
<content type='text'>
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098
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Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098
</pre>
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</content>
</entry>
<entry>
<title>[RegScavenger] Remove scavengeRegister</title>
<updated>2023-06-08T10:10:21+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-06-08T07:11:01+00:00</published>
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<id>c66c59242128ead025afc932bd812397d5ddf1f9</id>
<content type='text'>
All users have been converted to scavengeRegisterBackwards.

Differential Revision: https://reviews.llvm.org/D152425
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<pre>
All users have been converted to scavengeRegisterBackwards.

Differential Revision: https://reviews.llvm.org/D152425
</pre>
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</content>
</entry>
<entry>
<title>[RegScavenger] Change scavengeRegister to pick registers in allocation order</title>
<updated>2023-05-19T20:39:19+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-05-17T11:57:14+00:00</published>
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<id>8fcb4fa847f9b5c63520804f8035292fbe24fd75</id>
<content type='text'>
This matches what scavengeRegisterBackwards does.

This is in preparation for converting most uses of scavengeRegister to
scavengeRegisterBackwards, to reduce test case churn when that lands and
to help with bisection if anything goes wrong.

Differential Revision: https://reviews.llvm.org/D150792
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<pre>
This matches what scavengeRegisterBackwards does.

This is in preparation for converting most uses of scavengeRegister to
scavengeRegisterBackwards, to reduce test case churn when that lands and
to help with bisection if anything goes wrong.

Differential Revision: https://reviews.llvm.org/D150792
</pre>
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