This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned` and inserts necessary casts. The added `MCRegUnitToIndex` functor is used with `SparseSet`, `SparseMultiSet` and `IndexedMap` in a few places. `MCRegUnit` is opaque to users, so it didn't seem worth making it a full-fledged class like `Register`. Static type checking has detected one issue in `PrologueEpilogueInserter.cpp`, where `BitVector` created for `MCRegister` is indexed by both `MCRegister` and `MCRegUnit`. The number of casts could be reduced by using `IndexedMap` in more places and/or adding a `BitVector` adaptor, but the number of casts *per file* is still small and `IndexedMap` has limitations, so it didn't seem worth the effort. Pull Request: https://github.com/llvm/llvm-project/pull/167943
BreakFalseDeps picks the best register for undef operands if instructions have false dependency. The problem is if the instruction is close to the beginning of the function, ReachingDefAnalysis is over optimism to the unused registers, which results in collision with registers just defined in the caller. This patch changes the selection of undef register in an reverse order, which reduces the probability of register collisions between caller and callee. It brings improvement in some of our internal benchmarks with negligible effect on other benchmarks.
Many of these are indexing BitVectors or something where we can't using MCRegister and need the register number.
This reverts commit f8525030004f907cd108e7c18df255a6d3b23124. It was supposed to speed things up but llvm-compile-time-tracker.com showed a slight slow down.
Previously we called ignoreCSRForAllocationOrder on every alias of every CSR which was expensive on targets like AMDGPU which define a very large number of overlapping register tuples. On such targets it is simpler and faster to call ignoreCSRForAllocationOrder once for every physical register. Differential Revision: https://reviews.llvm.org/D146735
Change the implementation of getLastCalleeSavedAlias to use RegUnits instead of register aliases. This is much faster on targets like AMDGPU which define a very large number of overlapping register tuples. No functional change intended. If PhysReg overlaps multiple CSRs then getLastCalleeSavedAlias(PhysReg) could conceivably return a different arbitrary one, but currently it is only used for some debug printing anyway. Differential Revision: https://reviews.llvm.org/D146734
D132080 introduced a bug leading to `RegisterClassInfo` caches not getting invalidated when there was exactly one more CSR register added. Differential Revision: https://reviews.llvm.org/D132606