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<title>llvm-project.git/llvm/lib/CodeGen/RegAllocGreedy.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[CodeGen] Turn MCRegUnit into an enum class (NFC) (#167943)</title>
<updated>2025-11-16T17:46:44+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2025-11-16T17:46:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=97a60aa37a048155fec0c560fc51ed52dbd84e44'/>
<id>97a60aa37a048155fec0c560fc51ed52dbd84e44</id>
<content type='text'>
This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned`
and inserts necessary casts.
The added `MCRegUnitToIndex` functor is used with `SparseSet`,
`SparseMultiSet` and `IndexedMap` in a few places.

`MCRegUnit` is opaque to users, so it didn't seem worth making it a
full-fledged class like `Register`.

Static type checking has detected one issue in
`PrologueEpilogueInserter.cpp`, where `BitVector` created for
`MCRegister` is indexed by both `MCRegister` and `MCRegUnit`.

The number of casts could be reduced by using `IndexedMap` in more
places and/or adding a `BitVector` adaptor, but the number of casts *per
file* is still small and `IndexedMap` has limitations, so it didn't seem
worth the effort.

Pull Request: https://github.com/llvm/llvm-project/pull/167943</content>
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<pre>
This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned`
and inserts necessary casts.
The added `MCRegUnitToIndex` functor is used with `SparseSet`,
`SparseMultiSet` and `IndexedMap` in a few places.

`MCRegUnit` is opaque to users, so it didn't seem worth making it a
full-fledged class like `Register`.

Static type checking has detected one issue in
`PrologueEpilogueInserter.cpp`, where `BitVector` created for
`MCRegister` is indexed by both `MCRegister` and `MCRegUnit`.

The number of casts could be reduced by using `IndexedMap` in more
places and/or adding a `BitVector` adaptor, but the number of casts *per
file* is still small and `IndexedMap` has limitations, so it didn't seem
worth the effort.

Pull Request: https://github.com/llvm/llvm-project/pull/167943</pre>
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</content>
</entry>
<entry>
<title>[RegAllocGreedy] Use MCRegister instead of MCPhysReg. NFC (#167974)</title>
<updated>2025-11-13T23:26:35+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-11-13T23:26:35+00:00</published>
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<id>388ef6125006528683beffecd84bf17155efa43f</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Greedy: Take hints from copy to physical subreg (#160467)</title>
<updated>2025-10-02T14:28:38+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-10-02T14:28:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=11b0cf8fbeaf8b2384f3ab4d7f6fe97bc7d3db63'/>
<id>11b0cf8fbeaf8b2384f3ab4d7f6fe97bc7d3db63</id>
<content type='text'>
Previously this took hints from subregister extract of physreg,
like  %vreg.sub = COPY $physreg

This now also handles the rarer case:
  $physreg_sub = COPY %vreg

Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.</content>
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<pre>
Previously this took hints from subregister extract of physreg,
like  %vreg.sub = COPY $physreg

This now also handles the rarer case:
  $physreg_sub = COPY %vreg

Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.</pre>
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</content>
</entry>
<entry>
<title>Greedy: Use initializer list for recoloring candidates (NFC) (#160486)</title>
<updated>2025-10-02T14:22:20+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-10-02T14:22:20+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Greedy: Merge VirtRegMap queries into one use (NFC) (#160485)</title>
<updated>2025-10-02T14:06:54+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-10-02T14:06:54+00:00</published>
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<id>706b79002e21b571888db7f275bf5ed00e7cce41</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Greedy: Move physreg check when trying to recolor vregs (NFC) (#160484)</title>
<updated>2025-10-02T13:24:49+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-10-02T13:24:49+00:00</published>
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<id>c4e1bca407f4cca7644937c117890fad157fec4b</id>
<content type='text'>
Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.</content>
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<pre>
Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.</pre>
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</content>
</entry>
<entry>
<title>RegAllocGreedy: Check if copied lanes are live in trySplitAroundHintReg (#160424)</title>
<updated>2025-10-02T12:21:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-10-02T12:21:02+00:00</published>
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<id>3537e8abfa067013f01b53259fb2cc854d587dee</id>
<content type='text'>
For subregister copies, do a subregister live check instead of checking
the main range. Doesn't do much yet, the split analysis still does not
track live ranges.</content>
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<pre>
For subregister copies, do a subregister live check instead of checking
the main range. Doesn't do much yet, the split analysis still does not
track live ranges.</pre>
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</content>
</entry>
<entry>
<title>Greedy: Make trySplitAroundHintReg try to match hints with subreg copies (#160294)</title>
<updated>2025-09-26T15:14:38+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-26T15:14:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=129394e3f2cfb7fbac7b71a968a38328c82e9c8d'/>
<id>129394e3f2cfb7fbac7b71a968a38328c82e9c8d</id>
<content type='text'>
This is essentially the same patch as
116ca9522e89f1e4e02676b5bbe505e80c4d4933;
when trying to match a physreg hint, try to find a compatible physreg if
there is
a subregister copy. This has the slight difference of using getSubReg on
the hint
instead of getMatchingSuperReg (the other use should also use getSubReg
instead,
it's faster).

At the moment this turns out to have very little effect. The adjacent
code needs
better handling of subregisters, so continue adding this piecemeal. The
X86 test
shows a net reduction in real instructions, plus a few new kills.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is essentially the same patch as
116ca9522e89f1e4e02676b5bbe505e80c4d4933;
when trying to match a physreg hint, try to find a compatible physreg if
there is
a subregister copy. This has the slight difference of using getSubReg on
the hint
instead of getMatchingSuperReg (the other use should also use getSubReg
instead,
it's faster).

At the moment this turns out to have very little effect. The adjacent
code needs
better handling of subregisters, so continue adding this piecemeal. The
X86 test
shows a net reduction in real instructions, plus a few new kills.</pre>
</div>
</content>
</entry>
<entry>
<title>Greedy: Simplify collectHintInfo using MachineOperands. NFCI. (#159724)</title>
<updated>2025-09-22T10:48:52+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-09-22T10:48:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=cecdff92838f3c049548e3445a15d8c9c7a49205'/>
<id>cecdff92838f3c049548e3445a15d8c9c7a49205</id>
<content type='text'>
If a COPY uses Reg but only in an implicit operand then the new
implementation ignores it but the old implementation would have treated
it as a copy of Reg. Probably this case never occurs in practice. Other
than that, this patch is NFC.

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
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<pre>
If a COPY uses Reg but only in an implicit operand then the new
implementation ignores it but the old implementation would have treated
it as a copy of Reg. Probably this case never occurs in practice. Other
than that, this patch is NFC.

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
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</content>
</entry>
<entry>
<title>Greedy: Take copy hints involving subregisters (#159570)</title>
<updated>2025-09-19T00:37:36+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-19T00:37:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=116ca9522e89f1e4e02676b5bbe505e80c4d4933'/>
<id>116ca9522e89f1e4e02676b5bbe505e80c4d4933</id>
<content type='text'>
Previously this would only accept full copy hints. This relaxes
this to accept some subregister copies. Specifically, this now
accepts:
  - Copies to/from physical registers if there is a compatible
    super register
  - Subreg-to-subreg copies

This has the potential to repeatedly add the same hint to the
hint vector, but not sure if that's a real problem.</content>
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<pre>
Previously this would only accept full copy hints. This relaxes
this to accept some subregister copies. Specifically, this now
accepts:
  - Copies to/from physical registers if there is a compatible
    super register
  - Subreg-to-subreg copies

This has the potential to repeatedly add the same hint to the
hint vector, but not sure if that's a real problem.</pre>
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</content>
</entry>
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