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<title>llvm-project.git/llvm/lib/CodeGen/RDFRegisters.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[CodeGen] Turn MCRegUnit into an enum class (NFC) (#167943)</title>
<updated>2025-11-16T17:46:44+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2025-11-16T17:46:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=97a60aa37a048155fec0c560fc51ed52dbd84e44'/>
<id>97a60aa37a048155fec0c560fc51ed52dbd84e44</id>
<content type='text'>
This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned`
and inserts necessary casts.
The added `MCRegUnitToIndex` functor is used with `SparseSet`,
`SparseMultiSet` and `IndexedMap` in a few places.

`MCRegUnit` is opaque to users, so it didn't seem worth making it a
full-fledged class like `Register`.

Static type checking has detected one issue in
`PrologueEpilogueInserter.cpp`, where `BitVector` created for
`MCRegister` is indexed by both `MCRegister` and `MCRegUnit`.

The number of casts could be reduced by using `IndexedMap` in more
places and/or adding a `BitVector` adaptor, but the number of casts *per
file* is still small and `IndexedMap` has limitations, so it didn't seem
worth the effort.

Pull Request: https://github.com/llvm/llvm-project/pull/167943</content>
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<pre>
This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned`
and inserts necessary casts.
The added `MCRegUnitToIndex` functor is used with `SparseSet`,
`SparseMultiSet` and `IndexedMap` in a few places.

`MCRegUnit` is opaque to users, so it didn't seem worth making it a
full-fledged class like `Register`.

Static type checking has detected one issue in
`PrologueEpilogueInserter.cpp`, where `BitVector` created for
`MCRegister` is indexed by both `MCRegister` and `MCRegUnit`.

The number of casts could be reduced by using `IndexedMap` in more
places and/or adding a `BitVector` adaptor, but the number of casts *per
file* is still small and `IndexedMap` has limitations, so it didn't seem
worth the effort.

Pull Request: https://github.com/llvm/llvm-project/pull/167943</pre>
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</content>
</entry>
<entry>
<title>[RDF] Rename RegisterId field in RegisterRef Reg-&gt;Id. NFC (#168154)</title>
<updated>2025-11-15T02:33:50+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-11-15T02:33:50+00:00</published>
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<id>5442aa1853df1ab4406628d7e6ee4f785044c11d</id>
<content type='text'>
Not all RegisterId values are registers, so Id is a more appropriate
name.

Use asMCReg() in some places that assumed it was a register.</content>
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<pre>
Not all RegisterId values are registers, so Id is a more appropriate
name.

Use asMCReg() in some places that assumed it was a register.</pre>
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</content>
</entry>
<entry>
<title>[RDF] RegisterRef/RegisterId improvements. NFC (#168030)</title>
<updated>2025-11-14T18:30:25+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-11-14T18:30:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7108b12f6b678ba47adc485f814598bf6842b1ca'/>
<id>7108b12f6b678ba47adc485f814598bf6842b1ca</id>
<content type='text'>
RegisterId can represent a physical register, a MCRegUnit, or
an index into a side structure that stores register masks. These 3
types were encoded by using the physical reg, stack slot, and
virtual register encoding partitions from the Register class.
This encoding scheme alias wasn't well contained so
Register::index2StackSlot and Register::stackSlotIndex appeared
in multiple places.

This patch gives RegisterRef its own encoding defines and separates
it from Register.

I've removed the generic idx() method in favor of getAsMCReg(),
getAsMCRegUnit(), and getMaskIdx() for some degree of type safety.

Some places used the RegisterId field of RegisterRef directly as a
register. Those have been updated to use getAsMCReg.
    
Some special cases for RegisterId 0 have been removed as it can
be treated like a MCRegister by existing code.
    
I think I want to rename the Reg field of RegisterRef to Id, but
I'll do that in another patch.
    
Additionally, callers of the RegisterRef constructor need to be
audited for implicit conversions from Register/MCRegister
to unsigned.</content>
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<pre>
RegisterId can represent a physical register, a MCRegUnit, or
an index into a side structure that stores register masks. These 3
types were encoded by using the physical reg, stack slot, and
virtual register encoding partitions from the Register class.
This encoding scheme alias wasn't well contained so
Register::index2StackSlot and Register::stackSlotIndex appeared
in multiple places.

This patch gives RegisterRef its own encoding defines and separates
it from Register.

I've removed the generic idx() method in favor of getAsMCReg(),
getAsMCRegUnit(), and getMaskIdx() for some degree of type safety.

Some places used the RegisterId field of RegisterRef directly as a
register. Those have been updated to use getAsMCReg.
    
Some special cases for RegisterId 0 have been removed as it can
be treated like a MCRegister by existing code.
    
I think I want to rename the Reg field of RegisterRef to Id, but
I'll do that in another patch.
    
Additionally, callers of the RegisterRef constructor need to be
audited for implicit conversions from Register/MCRegister
to unsigned.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Add TRI::regunits() iterating over all register units (NFC) (#167901)</title>
<updated>2025-11-13T17:27:35+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2025-11-13T17:27:35+00:00</published>
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<id>d1cc1376a08f23eebc74f564782862e19958d786</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[CodeGen] Use MCRegUnit in more places (NFC) (#167578)</title>
<updated>2025-11-11T22:08:50+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2025-11-11T22:08:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=10679307189fb5b51980acd33ae14d70345c6c75'/>
<id>10679307189fb5b51980acd33ae14d70345c6c75</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Remove static member functions Register::stackSlot2Index/isStackSlot. NFC</title>
<updated>2025-02-20T05:54:43+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-02-20T05:54:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=92ddbbd89fa2a904119267d3565bed8e95f4f8e2'/>
<id>92ddbbd89fa2a904119267d3565bed8e95f4f8e2</id>
<content type='text'>
Migrate the few users to the nonstatic member functions.
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<pre>
Migrate the few users to the nonstatic member functions.
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Set regunitmasks for leaf regs to all instead of none</title>
<updated>2023-08-14T14:22:35+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-08-14T13:08:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6551cfa8eb2960dbc27e2882b204c4e0aff0109f'/>
<id>6551cfa8eb2960dbc27e2882b204c4e0aff0109f</id>
<content type='text'>
This simplifies every use of MCRegUnitMaskIterator.

Differential Revision: https://reviews.llvm.org/D157864
</content>
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<pre>
This simplifies every use of MCRegUnitMaskIterator.

Differential Revision: https://reviews.llvm.org/D157864
</pre>
</div>
</content>
</entry>
<entry>
<title>[MC] Use regunits instead of MCRegUnitIterator. NFC.</title>
<updated>2023-06-16T11:21:32+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-06-16T10:01:29+00:00</published>
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<id>da7892f7295f31b46486418e2abf15334db96cbb</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D153122
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<pre>
Differential Revision: https://reviews.llvm.org/D153122
</pre>
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</content>
</entry>
<entry>
<title>[MC] Add MCRegisterInfo::regunits for iteration over register units</title>
<updated>2023-06-16T02:39:50+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2023-05-21T01:28:33+00:00</published>
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<id>aa2d0fbc30d948dc9ce7d312ae4c56467fa57932</id>
<content type='text'>
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098
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<pre>
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098
</pre>
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</content>
</entry>
<entry>
<title>[RDF] Allow individual units in PhysicalRegisterInfo::alias</title>
<updated>2023-06-13T21:08:19+00:00</updated>
<author>
<name>Krzysztof Parzyszek</name>
<email>kparzysz@quicinc.com</email>
</author>
<published>2023-06-03T17:32:45+00:00</published>
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</pre>
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