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<title>llvm-project.git/llvm/lib/CodeGen/PeepholeOptimizer.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[CodeGen] Add "override" where appropriate (NFC) (#164571)</title>
<updated>2025-10-22T13:51:08+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-10-22T13:51:08+00:00</published>
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<id>6bee6b2090a7cd0dedbc0af789a7cb4648e974f2</id>
<content type='text'>
Note that "override" makes "virtual" redundant.

Identified with modernize-use-override.</content>
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<pre>
Note that "override" makes "virtual" redundant.

Identified with modernize-use-override.</pre>
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</entry>
<entry>
<title>PeepholeOpt: Fix losing subregister indexes on full copies (#161310)</title>
<updated>2025-10-02T04:36:47+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-10-02T04:36:47+00:00</published>
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<content type='text'>
Previously if we had a subregister extract reading from a
full copy, the no-subregister incoming copy would overwrite
the DefSubReg index of the folding context.

There's one ugly rvv regression, but it's a downstream
issue of this; an unnecessary same class reg-to-reg full copy
was avoided.</content>
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<pre>
Previously if we had a subregister extract reading from a
full copy, the no-subregister incoming copy would overwrite
the DefSubReg index of the folding context.

There's one ugly rvv regression, but it's a downstream
issue of this; an unnecessary same class reg-to-reg full copy
was avoided.</pre>
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</content>
</entry>
<entry>
<title>PeepholeOpt: Try to constrain uses to support subregister (#161338)</title>
<updated>2025-09-30T15:18:51+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-30T15:18:51+00:00</published>
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<id>981122696701d3c3897af267afd73bbefa61c3d4</id>
<content type='text'>
This allows removing a special case hack in ARM. ARM's implementation
of getExtractSubregLikeInputs has the strange property that it reports
a register with a class that does not support the reported subregister
index. We can however reconstrain the register to support this usage.

This is an alternative to #159600. I've included the test, but
the output is different. In this case version the VMOVSR is
replaced with an ordinary subregister extract copy.</content>
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<pre>
This allows removing a special case hack in ARM. ARM's implementation
of getExtractSubregLikeInputs has the strange property that it reports
a register with a class that does not support the reported subregister
index. We can however reconstrain the register to support this usage.

This is an alternative to #159600. I've included the test, but
the output is different. In this case version the VMOVSR is
replaced with an ordinary subregister extract copy.</pre>
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</content>
</entry>
<entry>
<title>PeepholeOpt: Use initializer list (#160898)</title>
<updated>2025-09-26T15:38:09+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-26T15:38:09+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[CodeGen] Remove unused includes (NFC) (#141320)</title>
<updated>2025-05-24T07:00:00+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-05-24T07:00:00+00:00</published>
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<id>3bc174ba772c551352004417c11c35503d6283ad</id>
<content type='text'>
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.</content>
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<pre>
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.</pre>
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</content>
</entry>
<entry>
<title>[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (#140002)</title>
<updated>2025-05-22T15:07:52+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-22T15:07:52+00:00</published>
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<id>1fdf02ad5a4ca155017eea22688365a20aab077c</id>
<content type='text'>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</content>
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<pre>
Add per-property has&lt;Prop&gt;/set&lt;Prop&gt;/reset&lt;Prop&gt; functions to
MachineFunctionProperties.</pre>
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</content>
</entry>
<entry>
<title>[llvm] Remove redundant control flow (NFC) (#138304)</title>
<updated>2025-05-02T17:34:25+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-05-02T17:34:25+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>PeepholeOpt: Do not skip reg_sequence sources with subregs (#125667)</title>
<updated>2025-03-13T14:49:16+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-13T14:49:16+00:00</published>
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<id>c3c97eab12746f206e695846d327ffba132afa49</id>
<content type='text'>
Contrary to the comment, this particular code is not responsible
for handling any composes that may be required, and unhandled cases
are already rejected later. Lift this restriction to permit composes
and reg_sequence subregisters later.</content>
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<pre>
Contrary to the comment, this particular code is not responsible
for handling any composes that may be required, and unhandled cases
are already rejected later. Lift this restriction to permit composes
and reg_sequence subregisters later.</pre>
</div>
</content>
</entry>
<entry>
<title>PeepholeOpt: Remove subreg def check for bitcast (#130086)</title>
<updated>2025-03-07T00:44:08+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-07T00:44:08+00:00</published>
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<id>c22db56d7766fe704298b81b548fa6004a9d312c</id>
<content type='text'>
Subregister defs are illegal in SSA. Surprisingly this enables folding
into subregister insert patterns in one test.</content>
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<pre>
Subregister defs are illegal in SSA. Surprisingly this enables folding
into subregister insert patterns in one test.</pre>
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</content>
</entry>
<entry>
<title>PeepholeOpt: Remove subreg def check for insert_subreg (#130085)</title>
<updated>2025-03-07T00:40:51+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-07T00:40:51+00:00</published>
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</pre>
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