This is supposed to match ValT aka Register.

When running early-tailduplication we've seen problems with machine
verifier errors due to register class mismatches after doing the machine
SSA updates.

Typical scenario is that there is a PHI node and another instruction
that is using the same vreg:

   %othervreg:otherclass = PHI %vreg:origclass, %bb
   MInstr %vreg:origclass

but then after TailDuplicator::tailDuplicateAndUpdate we get

   %othervreg:otherclass = PHI %vreg:origclass, %bb, ...
   MInstr %othervreg:otherclass

Such rewrites are only valid if 'otherclass' is equal to (or a subclass
of) 'origclass'.

The solution here is based on adding a COPY instruction to make sure we
satisfy constraints given by 'MInstr' in the example. So if 'otherclass'
isn't equal to (or a subclass of) 'origclass' we insert a copy after the
PHI like this:

   %othervreg:otherclass = PHI %vreg:origclass, %bb, ...
   %newvreg:origclass = COPY %othervreg:otherclass
   MInstr %newvreg:origclass

A special case is when it is possible to constrain the register class
instead of inserting a COPY. We currently prefer to constrain the
register class instead of inserting a COPY, even if it is a bit unclear
if that always is better (considering register pressure for the
constrained class etc.).

Fixes: https://github.com/llvm/llvm-project/issues/62712

When initializing MachineSSAUpdater save all attributes of current
virtual register and create new virtual registers with same attributes.
Now new virtual registers have same both register class or bank and LLT.
Previously new virtual registers had same register class but LLT was not
set (LLT was set to default/empty LLT).
Required by GlobalISel for AMDGPU, new 'lane mask' virtual registers
created by MachineSSAUpdater need to have both register class and LLT.

patch 4 from: https://github.com/llvm/llvm-project/pull/73337

It looks like it causes buildbot failures.
As an example: https://lab.llvm.org/buildbot/#/builders/121/builds/20364

Revert to investigate...

This reverts commit 6bf27918144cb843cf5ae9a93cb5f936730f3cce.

GetValueInMiddleOfBlock uses result of GetValueAtEndOfBlockInternal if there is no value
defined for current basic block.

If there is already a value it tries (in this order):

to find single register coming from all predecessors
find existing phi node which matches our incoming registers
build new phi.
The compile time improvement is to use current available value if
it is defined out of current BB or it is a PHI register.
This is due to it can be used in the middle basic block.

Reviewed By: sameerds
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D126523

Prior to this patch, tail duplication handled debug info poorly -
specifically, debug instructions would be dropped instead of being set
undef, potentially extending the lifetimes of prior debug values that
should be killed. The pass was also very aggressive with dropping debug
info, dropping debug info even when the SSA value it referred to was
still present. This patch attempts to handle debug info more carefully,
checking to see whether each affected debug value can still be live,
setting it undef if not.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D106875

Looking at the Doxygen-generated documentation for the llvm namespace
currently shows all sorts of random comments from different parts of the
codebase. These are mostly caused by:

- File doc comments that aren't marked with \file, so they're attached to
  the next declaration, which is usually "namespace llvm {".
- Class doc comments placed before the namespace rather than before the
  class.
- Code comments before the namespace that (in my opinion) shouldn't be
  extracted by doxygen at all.

This commit fixes these comments. The generated doxygen documentation now
has proper docs for several classes and files, and the docs for the llvm
and llvm::detail namespaces are now empty.

Reviewed By: thakis, mizvekov

Differential Revision: https://reviews.llvm.org/D96736