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<title>llvm-project.git/llvm/lib/CodeGen/MachineRegisterInfo.cpp, branch users/fmayer/spr/compiler-rt-ubsan-leave-bufferedstacktrace-uninit</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[CodeGen] Allocate RegAllocHints map lazily (#102186)</title>
<updated>2024-08-07T05:56:32+00:00</updated>
<author>
<name>Alexis Engelke</name>
<email>engelke@in.tum.de</email>
</author>
<published>2024-08-07T05:56:32+00:00</published>
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<id>41491c77231e9d389ef18593be1fab4f4e810e88</id>
<content type='text'>
This hint map is not required whenever a new register is added, in fact,
at -O0, it is not used at all. Growing this map is quite expensive, as
SmallVectors are not trivially copyable.

Grow this map only when hints are actually added to avoid multiple grows
and grows when no hints are added at all.</content>
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<pre>
This hint map is not required whenever a new register is added, in fact,
at -O0, it is not used at all. Growing this map is quite expensive, as
SmallVectors are not trivially copyable.

Grow this map only when hints are actually added to avoid multiple grows
and grows when no hints are added at all.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove target SubRegLiveness flags (#95437)</title>
<updated>2024-06-14T07:51:56+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-06-14T07:51:56+00:00</published>
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<id>706e1975400b3f30bd406b694bb711a7c7dbe1c4</id>
<content type='text'>
This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget-&gt;enableSubRegLiveness()`
has been changed to `MRI-&gt;subRegLivenessEnabled()` to make sure the
option properly applies.</content>
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<pre>
This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget-&gt;enableSubRegLiveness()`
has been changed to `MRI-&gt;subRegLivenessEnabled()` to make sure the
option properly applies.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove unused MachineRegisterInfo methods</title>
<updated>2024-03-11T15:42:24+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-03-11T15:36:22+00:00</published>
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<id>575ca6744b755f75799c1d092f56953e776a80a6</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770)</title>
<updated>2024-03-11T15:35:05+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-03-11T15:35:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=63a5dc4aedaf8a4b26e536afb22612b4d69100bf'/>
<id>63a5dc4aedaf8a4b26e536afb22612b4d69100bf</id>
<content type='text'>
MachineRegisterInfo already knows the MF so there is no need to pass it
in as an argument.</content>
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<pre>
MachineRegisterInfo already knows the MF so there is no need to pass it
in as an argument.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)</title>
<updated>2024-02-05T13:07:01+00:00</updated>
<author>
<name>Petar Avramovic</name>
<email>Petar.Avramovic@amd.com</email>
</author>
<published>2024-02-05T13:07:01+00:00</published>
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<id>06f711a906be85e141bcce9a88ab304dc81e74ef</id>
<content type='text'>
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.

TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.

patch 3 from: https://github.com/llvm/llvm-project/pull/73337</content>
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<pre>
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.

TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.

patch 3 from: https://github.com/llvm/llvm-project/pull/73337</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#79274)</title>
<updated>2024-01-24T11:18:34+00:00</updated>
<author>
<name>Petar Avramovic</name>
<email>Petar.Avramovic@amd.com</email>
</author>
<published>2024-01-24T11:18:34+00:00</published>
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<id>c46109d0d78863ff5e4e23c8f9fd85eb1220a42e</id>
<content type='text'>
Reverts llvm/llvm-project#78482</content>
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<pre>
Reverts llvm/llvm-project#78482</pre>
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</content>
</entry>
<entry>
<title>AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#78482)</title>
<updated>2024-01-24T10:58:32+00:00</updated>
<author>
<name>Petar Avramovic</name>
<email>Petar.Avramovic@amd.com</email>
</author>
<published>2024-01-24T10:58:32+00:00</published>
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<id>91ddcba83ae4385fe771e918c096e6074b411de3</id>
<content type='text'>
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.

TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.

patch 3 from: https://github.com/llvm/llvm-project/pull/73337</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.

TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.

patch 3 from: https://github.com/llvm/llvm-project/pull/73337</pre>
</div>
</content>
</entry>
<entry>
<title>[ADT] Rename llvm::erase_value to llvm::erase (NFC) (#70156)</title>
<updated>2023-10-25T06:03:13+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2023-10-25T06:03:13+00:00</published>
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<id>f9306f6de3bd19a2dcacd64566852a5f92c86e77</id>
<content type='text'>
C++20 comes with std::erase to erase a value from std::vector.  This
patch renames llvm::erase_value to llvm::erase for consistency with
C++20.

We could make llvm::erase more similar to std::erase by having it
return the number of elements removed, but I'm not doing that for now
because nobody seems to care about that in our code base.

Since there are only 50 occurrences of erase_value in our code base,
this patch replaces all of them with llvm::erase and deprecates
llvm::erase_value.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
C++20 comes with std::erase to erase a value from std::vector.  This
patch renames llvm::erase_value to llvm::erase for consistency with
C++20.

We could make llvm::erase more similar to std::erase by having it
return the number of elements removed, but I'm not doing that for now
because nobody seems to care about that in our code base.

Since there are only 50 occurrences of erase_value in our code base,
this patch replaces all of them with llvm::erase and deprecates
llvm::erase_value.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] MachineRegisterInfo::constrainRegAttrs - add explicit auto reference to prevent copy.</title>
<updated>2023-08-13T13:12:26+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2023-08-13T13:12:20+00:00</published>
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<id>f793d99b1172cd0c1a3415473f982f2d4f089ced</id>
<content type='text'>
Fixes static analysis warning
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<pre>
Fixes static analysis warning
</pre>
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</content>
</entry>
<entry>
<title>[MC] Simplify uses of subregs/superregs. NFC.</title>
<updated>2023-04-18T13:14:07+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-04-18T13:12:14+00:00</published>
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<id>c30c5f0122243326f89c0f0e9e78118ff34ca9ed</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
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