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<title>llvm-project.git/llvm/lib/CodeGen/MachineLoopUtils.cpp, branch users/mingmingl-llvm/section-prefix</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[CodeGen] Avoid repeated hash lookups (NFC) (#124078)</title>
<updated>2025-01-23T16:46:19+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-01-23T16:46:19+00:00</published>
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<pre>
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</entry>
<entry>
<title>Fix an unused-variable warning in release build, NFC.</title>
<updated>2022-06-19T18:52:00+00:00</updated>
<author>
<name>Haojian Wu</name>
<email>hokein.wu@gmail.com</email>
</author>
<published>2022-06-19T18:52:00+00:00</published>
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<pre>
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</entry>
<entry>
<title>[MachinePipeliner] Handle failing constrainRegClass</title>
<updated>2022-06-19T17:55:19+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2022-06-19T17:55:19+00:00</published>
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<content type='text'>
The included test hits a verifier problems as one of the instructions:
```
%113:tgpreven, %114:tgprodd = MVE_VMLSLDAVas16 %12:tgpreven(tied-def 0), %11:tgprodd(tied-def 1), %7:mqpr, %8:mqpr, 0, $noreg, $noreg
```
Has two inputs that come from different PHIs with the same base reg, but
conflicting regclasses:
```
%11:tgprodd = PHI %103:gpr, %bb.1, %16:gpr, %bb.2
%12:tgpreven = PHI %103:gpr, %bb.1, %17:gpr, %bb.2
```

The MachinePipeliner would attempt to use %103 for both the %11 and %12
operands in the prolog, constraining the register class to the common
subset of both. Unfortunately there are no registers that are both odd
and even, so the second constrainRegClass fails. Fix this situation by
inserting a COPY for the second if the call to constrainRegClass fails.

The register allocation can then fold that extra copy away. The register
allocation of Q regs changed with this test, but the R regs were the
same and no new instructions are needed in the final assembly.

Differential Revision: https://reviews.llvm.org/D127971
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<pre>
The included test hits a verifier problems as one of the instructions:
```
%113:tgpreven, %114:tgprodd = MVE_VMLSLDAVas16 %12:tgpreven(tied-def 0), %11:tgprodd(tied-def 1), %7:mqpr, %8:mqpr, 0, $noreg, $noreg
```
Has two inputs that come from different PHIs with the same base reg, but
conflicting regclasses:
```
%11:tgprodd = PHI %103:gpr, %bb.1, %16:gpr, %bb.2
%12:tgpreven = PHI %103:gpr, %bb.1, %17:gpr, %bb.2
```

The MachinePipeliner would attempt to use %103 for both the %11 and %12
operands in the prolog, constraining the register class to the common
subset of both. Unfortunately there are no registers that are both odd
and even, so the second constrainRegClass fails. Fix this situation by
inserting a COPY for the second if the call to constrainRegClass fails.

The register allocation can then fold that extra copy away. The register
allocation of Q regs changed with this test, but the R regs were the
same and no new instructions are needed in the final assembly.

Differential Revision: https://reviews.llvm.org/D127971
</pre>
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</content>
</entry>
<entry>
<title>[ModuloSchedule] Fix terminator update when peeling.</title>
<updated>2022-06-06T19:52:28+00:00</updated>
<author>
<name>Hendrik Greving</name>
<email>hgreving@google.com</email>
</author>
<published>2022-05-25T15:18:55+00:00</published>
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<id>a43d25734a46788da47a1a3786b3cd2bca540a72</id>
<content type='text'>
Fixes a bug of us not correctly updating the terminator of the loop's
preheader, if multiple terminating branch instructions are present.

This is tested through existing tests. The bug itself is hard or not
possible to get exposed with the upstream Hexagon backend, because
the machine pipeliner checks for an existing preheader, which is
defined as a block with only 1 edge into the header.

The condition of this bug is a block into the loop with more than 1
edge, and not every downstream target checks for an existing preheader.

Differential Revision: https://reviews.llvm.org/D126386
</content>
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<pre>
Fixes a bug of us not correctly updating the terminator of the loop's
preheader, if multiple terminating branch instructions are present.

This is tested through existing tests. The bug itself is hard or not
possible to get exposed with the upstream Hexagon backend, because
the machine pipeliner checks for an existing preheader, which is
defined as a block with only 1 edge into the header.

The condition of this bug is a block into the loop with more than 1
edge, and not every downstream target checks for an existing preheader.

Differential Revision: https://reviews.llvm.org/D126386
</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments</title>
<updated>2022-03-16T12:25:42+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2022-03-16T12:21:25+00:00</published>
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<id>37b378386eefab39ef570db6172a8b8e660d7bfb</id>
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</pre>
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</entry>
<entry>
<title>Cleanup codegen includes</title>
<updated>2022-03-16T07:43:00+00:00</updated>
<author>
<name>serge-sans-paille</name>
<email>sguelton@redhat.com</email>
</author>
<published>2022-03-15T09:54:19+00:00</published>
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<id>989f1c72e0f4236ac35a35cc9998ea34bc62d5cd</id>
<content type='text'>
This is a (fixed) recommit of https://reviews.llvm.org/D121169

after:  1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681
</content>
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<pre>
This is a (fixed) recommit of https://reviews.llvm.org/D121169

after:  1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Cleanup codegen includes"</title>
<updated>2022-03-10T12:59:22+00:00</updated>
<author>
<name>Nico Weber</name>
<email>thakis@chromium.org</email>
</author>
<published>2022-03-10T12:54:41+00:00</published>
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<id>a278250b0f85949d4f98e641786e5eb2b540c6b0</id>
<content type='text'>
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169
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<pre>
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169
</pre>
</div>
</content>
</entry>
<entry>
<title>Cleanup codegen includes</title>
<updated>2022-03-10T09:00:30+00:00</updated>
<author>
<name>serge-sans-paille</name>
<email>sguelton@redhat.com</email>
</author>
<published>2022-03-07T23:25:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7f230feeeac8a67b335f52bd2e900a05c6098f20'/>
<id>7f230feeeac8a67b335f52bd2e900a05c6098f20</id>
<content type='text'>
after:  1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169
</content>
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<pre>
after:  1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove unused function isRegLiveInExitBlocks (NFC)</title>
<updated>2021-01-13T05:43:48+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2021-01-13T05:43:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2c2d489b78c43072b65f3d8c88c91def4c69f320'/>
<id>2c2d489b78c43072b65f3d8c88c91def4c69f320</id>
<content type='text'>
The last use was removed on Jan 17, 2020 in commit
42350cd893a9cf6c199b17441dc2ba526c7cca71.
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<pre>
The last use was removed on Jan 17, 2020 in commit
42350cd893a9cf6c199b17441dc2ba526c7cca71.
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Fix a simple FIXME. NFC.</title>
<updated>2020-04-09T09:54:03+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2020-04-09T09:42:16+00:00</published>
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