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<title>llvm-project.git/llvm/lib/CodeGen/MachineInstr.cpp, branch users/mingmingl-llvm/section-prefix</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[GISel] Introduce MIFlags::InBounds (#150900)</title>
<updated>2025-07-30T11:01:23+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-07-30T11:01:23+00:00</published>
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<id>ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4</id>
<content type='text'>
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.</content>
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<pre>
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.

It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.

Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.

This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).

For SWDEV-516125.</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][LLVM][CodeGen] Refactor MachineInstr operand accessors (#137261)</title>
<updated>2025-05-01T14:45:22+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-01T14:45:22+00:00</published>
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<id>64f552cefacbb36ccb5f6df7b57f532bb63f0006</id>
<content type='text'>
- Change MachineInstr operand accessors to use `ArrayRef` internally to
slice the operand array into sub-arrays.
- Minor: remove unnecessary {} on `MachineInstrBuilder::add`.</content>
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<pre>
- Change MachineInstr operand accessors to use `ArrayRef` internally to
slice the operand array into sub-arrays.
- Minor: remove unnecessary {} on `MachineInstrBuilder::add`.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm] Call hash_combine_range with ranges (NFC) (#136511)</title>
<updated>2025-04-20T23:36:03+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-20T23:36:03+00:00</published>
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<id>b01e25debaf3fde3c76c9763e78e118a7da3d592</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Construct SmallVector with iterator ranges (NFC) (#136258)</title>
<updated>2025-04-18T17:26:48+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-18T17:26:48+00:00</published>
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<id>58774f1b1f98402c8d62cdde01c1adea067aaf96</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Prune headers and move code out of line for build efficiency, NFC (#135622)</title>
<updated>2025-04-15T05:23:18+00:00</updated>
<author>
<name>Reid Kleckner</name>
<email>rnk@google.com</email>
</author>
<published>2025-04-15T05:23:18+00:00</published>
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<id>2538c607e903a1fe0cfcacd5732235cc8ff3adf7</id>
<content type='text'>
I noticed these destructors taking time with -ftime-trace and moved some
of them for minor build efficiency improvements.

The main impact of moving destructors out of line is that it avoids
requiring container fields containing other types from being complete,
i.e. one can have uptr&lt;T&gt; or vector&lt;T&gt; as a field with an incomplete
type T, and that means we can reduce transitive includes, as with
LegalizerInfo.h.

Move expensive getDebugOperandsForReg template out-of-line. The
std::function instantiation shows up in time trace even if you don't use
the function.</content>
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<pre>
I noticed these destructors taking time with -ftime-trace and moved some
of them for minor build efficiency improvements.

The main impact of moving destructors out of line is that it avoids
requiring container fields containing other types from being complete,
i.e. one can have uptr&lt;T&gt; or vector&lt;T&gt; as a field with an incomplete
type T, and that means we can reduce transitive includes, as with
LegalizerInfo.h.

Move expensive getDebugOperandsForReg template out-of-line. The
std::function instantiation shows up in time trace even if you don't use
the function.</pre>
</div>
</content>
</entry>
<entry>
<title>[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)</title>
<updated>2025-03-27T01:25:59+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-03-27T01:25:59+00:00</published>
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<id>79e82b6f146e39b2498b9eb44033cde8659ba6b7</id>
<content type='text'>
The primary effect of this is that we get proper scalable sizes printed
by the assembler, but this may also enable proper aliasing analysis. I
don't see any test changes resulting from the later.

Getting the size is slightly tricky as we store the scalable size as a
non-scalable quantity in the object size field for the frame index. We
really should remove that hack at some point...

For the synthetic tuple spills and fills, I dropped the size from the
split loads and stores to avoid incorrect (overly large) sizes. We could
also divide by the NF factor if we felt like writing the code to do so.</content>
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<pre>
The primary effect of this is that we get proper scalable sizes printed
by the assembler, but this may also enable proper aliasing analysis. I
don't see any test changes resulting from the later.

Getting the size is slightly tricky as we store the scalable size as a
non-scalable quantity in the object size field for the frame index. We
really should remove that hack at some point...

For the synthetic tuple spills and fills, I dropped the size from the
split loads and stores to avoid incorrect (overly large) sizes. We could
also divide by the NF factor if we felt like writing the code to do so.</pre>
</div>
</content>
</entry>
<entry>
<title>IR, CodeGen: Add command line flags for dumping instruction addresses and debug locations.</title>
<updated>2025-02-27T23:45:55+00:00</updated>
<author>
<name>Peter Collingbourne</name>
<email>peter@pcc.me.uk</email>
</author>
<published>2025-02-27T23:45:55+00:00</published>
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<id>0ebf7b473a98a7433568d0a225d8b38767bdae50</id>
<content type='text'>
As previously discussed [1], it is sometimes useful to be able to see
instruction addresses and debug locations as part of IR dumps. The
same applies to MachineInstrs which already dump debug locations but
not addresses. Therefore add some flags that can be used to enable
dumping of this information.

[1] https://discourse.llvm.org/t/small-improvement-to-llvm-debugging-experience/79914

Reviewers: rnk

Reviewed By: rnk

Pull Request: https://github.com/llvm/llvm-project/pull/127944
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As previously discussed [1], it is sometimes useful to be able to see
instruction addresses and debug locations as part of IR dumps. The
same applies to MachineInstrs which already dump debug locations but
not addresses. Therefore add some flags that can be used to enable
dumping of this information.

[1] https://discourse.llvm.org/t/small-improvement-to-llvm-debugging-experience/79914

Reviewers: rnk

Reviewed By: rnk

Pull Request: https://github.com/llvm/llvm-project/pull/127944
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)</title>
<updated>2025-02-25T23:29:12+00:00</updated>
<author>
<name>Eli Friedman</name>
<email>efriedma@quicinc.com</email>
</author>
<published>2025-02-25T23:29:12+00:00</published>
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<id>1b39328d7440aa7a94af4083257ef1c2f9394887</id>
<content type='text'>
Even if an inline asm doesn't have memory effects, we can't assume it's
safe to speculate: it could trap, or cause undefined behavior. At the
LLVM IR level, this is handled correctly: we don't speculate inline asm
(unless it's marked "speculatable", but I don't think anyone does that).
Codegen also needs to respect this restriction.

This change stops Early If Conversion and similar passes from
speculating an INLINEASM MachineInstr.

Some uses of isSafeToMove probably could be switched to a different API:
isSafeToMove assumes you're hoisting, but we could handle some forms of
sinking more aggressively. But I'll leave that for a followup, if it
turns out to be relevant.

See also discussion on gcc bugtracker
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102150 .</content>
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<pre>
Even if an inline asm doesn't have memory effects, we can't assume it's
safe to speculate: it could trap, or cause undefined behavior. At the
LLVM IR level, this is handled correctly: we don't speculate inline asm
(unless it's marked "speculatable", but I don't think anyone does that).
Codegen also needs to respect this restriction.

This change stops Early If Conversion and similar passes from
speculating an INLINEASM MachineInstr.

Some uses of isSafeToMove probably could be switched to a different API:
isSafeToMove assumes you're hoisting, but we could handle some forms of
sinking more aggressively. But I'll leave that for a followup, if it
turns out to be relevant.

See also discussion on gcc bugtracker
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102150 .</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][LLVM] Remove unused `TargetIntrinsicInfo` class (#126003)</title>
<updated>2025-02-10T22:56:30+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-02-10T22:56:30+00:00</published>
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<id>0f674cce82da851961b3e59b1bd663919e17fb65</id>
<content type='text'>
Remove `TargetIntrinsicInfo` class as its practically unused (its pure
virtual with no subclasses) and its references in the code.</content>
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<pre>
Remove `TargetIntrinsicInfo` class as its practically unused (its pure
virtual with no subclasses) and its references in the code.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] NFC: Change order of checks in MachineInstr-&gt;isDead() (#124207)</title>
<updated>2025-01-24T15:23:22+00:00</updated>
<author>
<name>Jeffrey Byrnes</name>
<email>jeffrey.byrnes@amd.com</email>
</author>
<published>2025-01-24T15:23:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6c11b7e689c89ff46e4472810dd555434eab1010'/>
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<content type='text'>
[[Change-Id:
Ic349022bb99ef91f5396e462ade0366bc772ae02](https://github.com/llvm/llvm-project/pull/123531)](https://github.com/llvm/llvm-project/pull/123531)
moved isDead() from DeadMachineInstrElim to MachineInstr . In the
process of moving, I reordered the checks to improve chances of early
exit, but this has caused a slight increase in compile time.

This PR reverts back to the original order of checks.</content>
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<pre>
[[Change-Id:
Ic349022bb99ef91f5396e462ade0366bc772ae02](https://github.com/llvm/llvm-project/pull/123531)](https://github.com/llvm/llvm-project/pull/123531)
moved isDead() from DeadMachineInstrElim to MachineInstr . In the
process of moving, I reordered the checks to improve chances of early
exit, but this has caused a slight increase in compile time.

This PR reverts back to the original order of checks.</pre>
</div>
</content>
</entry>
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