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<title>llvm-project.git/llvm/lib/CodeGen/MachineInstr.cpp, branch users/koachan/spr/main.sparcias-enable-parseforallfeatures-in-matchoperandparserimpl</title>
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<entry>
<title>[GlobalIsel] Import GEP flags (#93850)</title>
<updated>2024-06-14T18:56:43+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-06-14T18:56:43+00:00</published>
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<id>b1f9440fa9286638bb1fe72a14d220770d1987cc</id>
<content type='text'>
https://github.com/llvm/llvm-project/pull/90824</content>
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<pre>
https://github.com/llvm/llvm-project/pull/90824</pre>
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</entry>
<entry>
<title>[CodeGen] Make the parameter TRI required in some functions. (#85968)</title>
<updated>2024-04-24T13:24:14+00:00</updated>
<author>
<name>Xu Zhang</name>
<email>simonzgx@gmail.com</email>
</author>
<published>2024-04-24T13:24:14+00:00</published>
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<id>f6d431f208c0fa48827eac40e7acf788346a9967</id>
<content type='text'>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</content>
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Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</pre>
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</content>
</entry>
<entry>
<title>[IR] Memory Model Relaxation Annotations (#78569)</title>
<updated>2024-04-24T06:52:25+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2024-04-24T06:52:25+00:00</published>
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<id>cf328ff96daf5e676fb51ac86e550af7fd689fec</id>
<content type='text'>
Implements the core/target-agnostic components of Memory Model
Relaxation Annotations.

RFC:
https://discourse.llvm.org/t/rfc-mmras-memory-model-relaxation-annotations/76361/5</content>
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<pre>
Implements the core/target-agnostic components of Memory Model
Relaxation Annotations.

RFC:
https://discourse.llvm.org/t/rfc-mmras-memory-model-relaxation-annotations/76361/5</pre>
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</content>
</entry>
<entry>
<title>[GlobalIsel] add trunc flags (#87045)</title>
<updated>2024-03-29T12:38:08+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-03-29T12:38:08+00:00</published>
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<id>84299df301dc07ea83fa8378051103195c3a7c65</id>
<content type='text'>
https://github.com/llvm/llvm-project/pull/85592</content>
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<pre>
https://github.com/llvm/llvm-project/pull/85592</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Add nneg and disjoint flags (#86650)</title>
<updated>2024-03-26T17:44:34+00:00</updated>
<author>
<name>Thorsten Schütt</name>
<email>schuett@gmail.com</email>
</author>
<published>2024-03-26T17:44:34+00:00</published>
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<id>da6cc4a24ff8953d51f7dc2c4974e8fc9089d693</id>
<content type='text'>
MachineInstr learned the new flags.</content>
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<pre>
MachineInstr learned the new flags.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Update for scalable MemoryType in MMO (#70452)</title>
<updated>2024-03-23T12:56:25+00:00</updated>
<author>
<name>Harvin Iriawan</name>
<email>25712785+harviniriawan@users.noreply.github.com</email>
</author>
<published>2024-03-23T12:56:25+00:00</published>
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<id>57146daeaaf366050dc913db910fcc2995a3e06d</id>
<content type='text'>
Remove getSizeOrUnknown call when MachineMemOperand is created.  For Scalable
TypeSize, the MemoryType created becomes a scalable_vector.

2 MMOs that have scalable memory access can then use the updated BasicAA that
understands scalable LocationSize.

Original Patch by Harvin Iriawan
Co-authored-by: David Green &lt;david.green@arm.com&gt;</content>
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Remove getSizeOrUnknown call when MachineMemOperand is created.  For Scalable
TypeSize, the MemoryType created becomes a scalable_vector.

2 MMOs that have scalable memory access can then use the updated BasicAA that
understands scalable LocationSize.

Original Patch by Harvin Iriawan
Co-authored-by: David Green &lt;david.green@arm.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Use LocationSize for MMO getSize (#84751)</title>
<updated>2024-03-17T18:15:56+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-03-17T18:15:56+00:00</published>
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<id>601e102bdb55e12a2f791e0d68fd6f81ffc21e21</id>
<content type='text'>
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</content>
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<pre>
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.</pre>
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</content>
</entry>
<entry>
<title>[Codegen] Change getSpillSize/getReloadSize to LocationSize. NFC (#82636)</title>
<updated>2024-02-25T16:22:57+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-02-25T16:22:57+00:00</published>
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<id>d6ded91121fa02837ef6c8c7f06d98ccf4a0fe16</id>
<content type='text'>
This is a small part of #70452, attempting to take a small simpler part
of it in isolation to simplify what remains. It changes the getSpillSize,
getFoldedSpillSize, getRestoreSize and getFoldedRestoreSize methods to return
optional&lt;LocationSize&gt; instead of unsigned. The code is intended to be the
same, keeping the optional&lt;&gt; to specify when there was no size found, with some
minor adjustments to make sure that unknown (~UINT64_C(0)) sizes are handled
sensibly.  Hopefully as more unsigned's are converted to LocationSize's the use
of ~UINT64_C(0) can be cleaned up too.</content>
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<pre>
This is a small part of #70452, attempting to take a small simpler part
of it in isolation to simplify what remains. It changes the getSpillSize,
getFoldedSpillSize, getRestoreSize and getFoldedRestoreSize methods to return
optional&lt;LocationSize&gt; instead of unsigned. The code is intended to be the
same, keeping the optional&lt;&gt; to specify when there was no size found, with some
minor adjustments to make sure that unknown (~UINT64_C(0)) sizes are handled
sensibly.  Hopefully as more unsigned's are converted to LocationSize's the use
of ~UINT64_C(0) can be cleaned up too.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm] Move CodeGenTypes library to its own directory (#79444)</title>
<updated>2024-01-25T17:01:31+00:00</updated>
<author>
<name>Nico Weber</name>
<email>thakis@chromium.org</email>
</author>
<published>2024-01-25T17:01:31+00:00</published>
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<id>184ca39529a93e69eb175861d7fff5fc79988e53</id>
<content type='text'>
Finally addresses https://reviews.llvm.org/D148769#4311232 :)

No behavior change.</content>
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<pre>
Finally addresses https://reviews.llvm.org/D148769#4311232 :)

No behavior change.</pre>
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</content>
</entry>
<entry>
<title>MachineVerifier: Reject extra non-register operands on instructions (#73758)</title>
<updated>2023-11-30T13:33:42+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2023-11-30T13:33:42+00:00</published>
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<id>c44dca15a4297eef3b9319a5e24f85267a099642</id>
<content type='text'>
We were allowing extra immediate arguments, and only bothering to check
if registers were implicit or not.

Also consolidate extra operand checks in verifier, to make this
testable. We had 3 different places checking if you were trying to build
an instruction with more operands than allowed by the definition. We had
an assertion in addOperand, a direct check in the MIRParser to avoid the
assertion, and the machine verifier checks. Remove the assert and parser
check so the verifier can provide a consistent verification experience,
which will also handle instructions modified in place.</content>
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<pre>
We were allowing extra immediate arguments, and only bothering to check
if registers were implicit or not.

Also consolidate extra operand checks in verifier, to make this
testable. We had 3 different places checking if you were trying to build
an instruction with more operands than allowed by the definition. We had
an assertion in addOperand, a direct check in the MIRParser to avoid the
assertion, and the machine verifier checks. Remove the assert and parser
check so the verifier can provide a consistent verification experience,
which will also handle instructions modified in place.</pre>
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</content>
</entry>
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